Mitchell J. Myjak

According to our database, Mitchell J. Myjak authored at least 10 papers between 2003 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Frequency-Programmable Miniaturized Radio Frequency Transmitter for Animal Tracking.

Jun Lu, Huidong Li, Chuan Tian, Mitchell J. Myjak, Jie Xiao, Brian J. Bellgraph, Samuel S. Cartmell, Zhiqun Daniel Deng

Sensors, 2021

2008

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance.

Mitchell J. Myjak, José G. Delgado-Frias

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

Medium-Grain Cells for Reconfigurable DSP Hardware.

Mitchell J. Myjak, José G. Delgado-Frias

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006

Superpipelined reconfigurable hardware for DSP.

Mitchell J. Myjak, José G. Delgado-Frias

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture.

Mitchell J. Myjak, Jonathan Larson, José G. Delgado-Frias

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005

A Symmetric Differential Clock Generator for Bit-Serial Hardware.

Mitchell J. Myjak, José G. Delgado-Frias

Proceedings of the 2005 International Conference on Computer Design, 2005

Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.

Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias

Proceedings of the 2005 International Conference on Computer Design, 2005

2004

Pipelined Multipliers for Reconfigurable Hardware.

Mitchell J. Myjak, José G. Delgado-Frias

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

H-Tree Interconnection Structure for Reconfigurable DSP Hardware.

Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

A Two-Level Reconfigurable Architecture for Digital Signal Processing.

Mitchell J. Myjak, José G. Delgado-Frias

Proceedings of the International Conference on VLSI, 2003