Mitchell A. Thornton
Orcid: 0000-0003-3559-9511Affiliations:
- Southern Methodist University, Dallas, Texas, USA
According to our database1,
Mitchell A. Thornton
authored at least 140 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on zbmath.org
-
on orcid.org
-
on engr.smu.edu
-
on dl.acm.org
On csauthors.net:
Bibliography
2024
CoRR, 2024
Designing a Photonic Physically Unclonable Function Having Resilience to Machine Learning Attacks.
CoRR, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
A Photonic Physically Unclonable Function's Resilience to Multiple-Valued Machine Learning Attacks.
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024
Proceedings of the IEEE International Conference on Acoustics, 2024
2023
CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques.
CoRR, 2023
Multiple-Valued Logic Physically Unclonable Function in Photonic Integrated Circuits.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023
Proceedings of the 52nd IEEE Applied Imagery Pattern Recognition Workshop, 2023
Proceedings of the 52nd IEEE Applied Imagery Pattern Recognition Workshop, 2023
2022
Proceedings of the IEEE International Systems Conference, 2022
A Side Channel Attack Detection System Using Processor Core Events and a Support Vector Machine.
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Side Channel Identification using Granger Time Series Clustering with Applications to Control Systems.
Proceedings of the 8th International Conference on Information Systems Security and Privacy, 2022
Proceedings of the 51st IEEE Applied Imagery Pattern Recognition Workshop, 2022
2021
Real-Time Edge Processing Detection of Malicious Attacks Using Machine Learning and Processor Core Events.
Proceedings of the IEEE International Systems Conference, 2021
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2021
Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus.
Proceedings of the IEEE Conference on Control Technology and Applications, 2021
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
Proceedings of the IEEE International Test Conference, 2020
Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Enhanced Automatic Modulation Classification using Deep Convolutional Latent Space Pooling.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
Keyboard Snooping from Mobile Phone Arrays with Mixed Convolutional and Recurrent Neural Networks.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019
2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
2017
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the Quantum Technology and Optimization Problems, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the Annual IEEE Systems Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 15th IEEE International Conference on Machine Learning and Applications, 2016
2015
IEEE Trans. Computers, 2015
Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.
J. Multiple Valued Log. Soft Comput., 2015
J. Multiple Valued Log. Soft Comput., 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015
2014
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79867-2, 2014
J. Multiple Valued Log. Soft Comput., 2014
IEICE Trans. Inf. Syst., 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE Frontiers in Education Conference, 2014
2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the IEEE Frontiers in Education Conference, 2013
Proceedings of the IEEE Frontiers in Education Conference, 2013
2012
J. Multiple Valued Log. Soft Comput., 2012
Proceedings of the 43rd ACM technical symposium on Computer science education, 2012
Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
Proceedings of the Encyclopedia of Cryptography and Security, 2nd Ed., 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
2010
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79815-3, 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
2009
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2<sup>k</sup>: Algorithms and Lookup Structures.
IEEE Trans. Computers, 2009
Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics.
J. Multiple Valued Log. Soft Comput., 2009
Proceedings of the ISMVL 2009, 2009
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©.
Proceedings of the ISMVL 2009, 2009
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009
2008
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility.
Int. J. Bus. Inf. Syst., 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008
A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers, ISBN: 978-1-59829-190-2, 2008
2007
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79779-8, 2007
J. Multiple Valued Log. Soft Comput., 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007
Proceedings of the Tenth IEEE International Symposium on High Assurance Systems Engineering (HASE 2007), 2007
Proceedings of the Forum on specification and Design Languages, 2007
2006
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79743-9, 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2<sup>k</sup>.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005
2004
J. Multiple Valued Log. Soft Comput., 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Test vector generation and classification using FSM traversals.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
2003
Parallel Process. Lett., 2003
Comput. Electr. Eng., 2003
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 2003 Design, 2003
2002
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.
VLSI Design, 2002
On-line Error Detection in a Carry-free Adder.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Low Power Optimization Techniques for BDD Mapped Finite State Machines.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of ASP-DAC 2001, 2001
Spectral techniques in VLSI CAD.
Kluwer, ISBN: 978-0-7923-7433-6, 2001
2000
Integr., 2000
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
ACM Trans. Design Autom. Electr. Syst., 1999
Proceedings of the 1999 Design, 1999
1998
Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum.
Proceedings of the 1998 workshop on Computer architecture education, 1998
1997
IEEE Trans. Computers, 1997
Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1993
Proceedings of the European Design Automation Conference 1993, 1993