Mirjana Stojilovic

Orcid: 0000-0001-5649-5020

According to our database1, Mirjana Stojilovic authored at least 35 papers between 2012 and 2024.

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Bibliography

2024
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs.
IEEE Access, 2024

2023
A Visionary Look at the Security of Reconfigurable Cloud Computing.
Proc. IEEE, December, 2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs.
J. Hardw. Syst. Secur., September, 2023

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

The Side-channel Metrics Cheat Sheet.
ACM Comput. Surv., 2023

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era.
ACM Comput. Surv., 2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Active Wire Fences for Multitenant FPGAs.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
The Side-Channel Metric Cheat Sheet.
IACR Cryptol. ePrint Arch., 2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks.
IEEE Access, 2022

FPGA-to-CPU Undervolting Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing.
IEEE Access, 2021

Deep Learning Detection of GPS Spoofing.
Proceedings of the Machine Learning, Optimization, and Data Science, 2021

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs.
IACR Cryptol. ePrint Arch., 2020

CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors.
IACR Cryptol. ePrint Arch., 2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
FPGA-Assisted Deterministic Routing for FPGAs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

A Machine Learning Approach for Power Gating the FPGA Routing Network.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Timing Violation Induced Faults in Multi-Tenant FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Parallel FPGA routing: Survey and challenges.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2013
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
Selective flexibility: Breaking the rigidity of datapath merging.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012


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