Mircea Vladutiu

Affiliations:
  • Politehnica University of Timisoara, Romania


According to our database1, Mircea Vladutiu authored at least 69 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Systolic Array Architecture for Educational Use.
Proceedings of the 27th International Conference on System Theory, Control and Computing, 2023

2020
Environmentally-Friendly Metrics for Evaluating the Performance of Deep Learning Models and Systems.
Proceedings of the Neural Information Processing - 27th International Conference, 2020

Efficient Implementation of a Self-sufficient Solar-Powered Real-Time Deep Learning-Based System.
Proceedings of the 21st EANN (Engineering Applications of Neural Networks) 2020 Conference, 2020

Deep Learning-Based Computer Vision Application with Multiple Built-In Data Science-Oriented Capabilities.
Proceedings of the 21st EANN (Engineering Applications of Neural Networks) 2020 Conference, 2020

2019
Agent-based simulations of payoff distribution in economic networks.
Soc. Netw. Anal. Min., 2019

Real-time identification of animals found in domestic areas of Europe.
Proceedings of the Twelfth International Conference on Machine Vision, 2019

Mobile application for receipt fraud detection based on optical character recognition.
Proceedings of the Twelfth International Conference on Machine Vision, 2019

2018
Simulating Payoff Distribution in Networks of Economic Agents.
Proceedings of the IEEE/ACM 2018 International Conference on Advances in Social Networks Analysis and Mining, 2018

2017
Simulating Trade in Economic Networks with TrEcSim.
Proceedings of the Network Intelligence Meets User Centered Social Media Networks [4th European Network Intelligence Conference, 2017

2015
Tolerance-based interaction: A new model targeting opinion formation and diffusion in social networks.
PeerJ Prepr., 2015

Evaluating the self-testing property of AES' finite field inversion units.
Proceedings of the 20th IEEE European Test Symposium, 2015

Bio-inspired redistribution of urban traffic flow using a social network approach.
Proceedings of the IEEE Congress on Evolutionary Computation, 2015

2014
Genetically Optimized Realistic Social Network Topology Inspired by Facebook.
Proceedings of the Online Social Media Analysis and Visualization, 2014

Social Cities: Redistribution of Traffic Flow in Cities Using a Social Network Approach.
Proceedings of the Soft Computing Applications, 2014

Heuristic Optimization of Wireless Sensor Networks Using Social Network Analysis.
Proceedings of the Soft Computing Applications, 2014

Parity-based Concurrent Error-detection Architecture Applied to the IDEA NXT Crypto-algorithm.
Proceedings of the Soft Computing Applications, 2014

2013
Collaborative environment for road traffic monitoring.
Proceedings of the 13th International Conference on ITS Telecommunications, 2013

Network Fidelity: A Metric to Quantify the Similarity and Realism of Complex Networks.
Proceedings of the 2013 International Conference on Cloud and Green Computing, Karlsruhe, Germany, September 30, 2013

2012
Simulated fault injection methodology for gate-level quantum circuit reliability assessment.
Simul. Model. Pract. Theory, 2012

HMail: A hybrid mailing system based on the collaboration between traditional and Peer-to-Peer mailing architectures.
Proceedings of the 7th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2012

High capacity steganographic algorithm based on payload adaptation and optimization.
Proceedings of the 7th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2012

Simplified selective fault tolerance technique for protection of selected inputs via triple modular redundancy systems.
Proceedings of the 7th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2012

Computer Arithmetic - Algorithms and Hardware Implementations.
Springer, ISBN: 978-3-642-18314-0, 2012

2011
Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Design of a Hierarchical Based DHT Overlay P2P Routing Algorithm.
Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

Decreasing Change Impact Using Smart LSB Pixel Mapping and Data Rearrangement.
Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

2010
Design Issues and Implementations for Floating-Point Divide-Add Fused.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Quantum circuit's reliability assessment with VHDL-based simulated fault injection.
Microelectron. Reliab., 2010

Adaptive vs. Self-adaptive Parameters for Evolving Quantum Circuits.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010

Performance Analysis for Genetic Quantum Circuit Synthesis.
Proceedings of the Artifical Intelligence and Soft Computing, 2010

Self-Adaptive mechanism for cache memory reliability improvement.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A high-speed AES architecture implementation.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Concurrent Error Detection for Multiplicative Inversion of Advanced Encryption Standard.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Built-in self test applicability for the non-linear operations of Advanced Encryption Standard.
Proceedings of the 5th International Symposium on Applied Computational Intelligence and Informatics, 2009

Intrusions Detection in Intelligent Agent-Based Non-traditional Grids.
Proceedings of the 2009 International Conference on Education Technology and Computer, 2009

Quantum Circuit Synthesis with Adaptive Parameters Control.
Proceedings of the Genetic Programming, 12th European Conference, 2009

Round-level concurrent error detection applied to Advanced Encryption Standard.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Genetic algorithm based quantum circuit synthesis with adaptive parameters control.
Proceedings of the IEEE Congress on Evolutionary Computation, 2009

2008
Redundancy at Link Level for Non-Traditional Grids Implemented with Intelligent Agents.
Proceedings of the NCM 2008, The Fourth International Conference on Networked Computing and Advanced Information Management, Gyeongju, Korea, September 2-4, 2008, 2008

Discussing Redundancy Issues in Intelligent Agent-Based Non-traditional Grids.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2008

Fault-Tolerant Memory Design and Partitioning Issues in Embryonics.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Floating point multiplication rounding schemes for interval arithmetic.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
A Genetic Algorithm Framework Applied to Quantum Circuit Synthesis.
Proceedings of the Nature Inspired Cooperative Strategies for Optimization (NICSO 2007), 2007

Design for dependability in emerging technologies.
ACM J. Emerg. Technol. Comput. Syst., 2007

Simulated Fault Injection for Quantum Circuits Based on Simulator Commands.
Proceedings of the 4th International Symposium on Applied Computational Intelligence and Informatics, 2007

Automatic Synthesis for Quantum Circuits Using Genetic Algorithms.
Proceedings of the Adaptive and Natural Computing Algorithms, 8th International Conference, 2007

Assessing quantum circuits reliability with mutant-based simulated fault injection.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.
Proceedings of the Proceedings 40th Annual Simulation Symposium (ANSS-40 2007), 2007

2006
Implementing quantum genetic algorithms: a solution based on Grover's algorithm.
Proceedings of the Third Conference on Computing Frontiers, 2006

A dependability perspective on emerging technologies.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Multiple-level concatenated coding in embryonics: a dependability analysis.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005

Survivability of Embryonic Memories: Analysis and Design Principles.
Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005

Improving quantum circuit dependability with reconfigurable quantum gate arrays.
Proceedings of the Second Conference on Computing Frontiers, 2005

Reliability assessment in embryonics inspired by fault-tolerant quantum computation.
Proceedings of the Second Conference on Computing Frontiers, 2005

The Bubble Bit Technique as Improvement of HDL-Based Quantum Circuits Simulation.
Proceedings of the Proceedings 38th Annual Simulation Symposium (ANSS-38 2005), 2005

2004
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints.
J. Electron. Test., 2004

Self-Repairing Embryonic Memory Arrays.
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation.
Proceedings of the First Conference on Computing Frontiers, 2004

2001
Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

A combined tree growing technique for block-test scheduling under power constraints.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Power-Constrained Block-Test List Scheduling.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

A comparison of classical scheduling approaches in power-constrained block-test scheduling.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

The left edge algorithm in block test scheduling under power constraints.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000


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