Miquel Moretó

According to our database, Miquel Moretó authored at least 138 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium.

Xavier Carril, Charalampos Kardaris, Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó

ACM Trans. Reconfigurable Technol. Syst., September, 2024

OpenPiton4HPC: Optimizing OpenPiton Toward High-Performance Manycores.

Neiel Leyva, Alireza Monemi, Noelia Oliete-Escuín, Guillem López-Paradís, Xabier Abancens, Jonathan Balkind, Enrique Vallejo, Miquel Moretó, Lluc Alvarez

IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

GenArchBench: A genomics benchmark suite for arm HPC processors.

Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó

Future Gener. Comput. Syst., 2024

A Mess of Memory System Benchmarking, Simulation and Application Profiling.

Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard

CoRR, 2024

Floating Point HUB Adder for RISC-V Sargantana Processor.

Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba

CoRR, 2024

A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator.

Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

WFA-FPGA: An efficient accelerator of the wavefront algorithm for short and long read genomics alignment.

Abbas Haghi, Santiago Marco-Sola, Lluc Alvarez, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó

Future Gener. Comput. Syst., December, 2023

Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023).

Mahdi Nikdast, Miquel Moretó, Masoumeh Ebrahimi, Sujay Deb

IEEE Des. Test, December, 2023

WFA-GPU: gap-affine pairwise read-alignment using GPUs.

Quim Aguado-Puig, Max Doblas, Christos Matzoros, Antonio Espinosa, Juan Carlos Moure, Santiago Marco-Sola, Miquel Moretó

Bioinform., December, 2023

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code.

Lorién López-Villellas, Carl Christian Kjelgaard Mikkelsen, Juan José Galano-Frutos, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó, Javier Sancho, Pablo García-Risueño

Comput. Phys. Commun., July, 2023

Functional Verification of a RISC-V Vector Accelerator.

Víctor Jiménez, Mario Rodríguez, Marc Domínguez, Josep Sans, Ivan Diaz, Luca Valente, Vito Luca Guglielmi, Josue V. Quiroga, R. Ignacio Genovese, Nehir Sönmez, Oscar Palomar, Miquel Moretó

IEEE Des. Test, June, 2023

Adaptive Power Shifting for Power-Constrained Heterogeneous Systems.

Cristobal Ortega, Lluc Alvarez, Alper Buyuktosunoglu, Ramon Bertran, Todd Rosedahl, Pradip Bose, Miquel Moretó

IEEE Trans. Computers, March, 2023

Optimal gap-affine alignment in <i>O</i>(<i>s</i>) space.

Santiago Marco-Sola, Jordan M. Eizenga, Andrea Guarracino, Benedict Paten, Erik Garrison, Miquel Moretó

Bioinform., February, 2023

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor.

Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2023

SpChar: Characterizing the Sparse Puzzle via Decision Trees.

Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó

CoRR, 2023

Characterization of a Coherent Hardware Accelerator Framework for SoCs.

Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors.

Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

OpenPiton Optimizations Towards High Performance Manycores.

Neiel Leyva, Alireza Monemi, Noelia Oliete-Escuín, Guillem López-Paradís, Xabier Abancens, Jonathan Balkind, Enrique Vallejo, Miquel Moretó, Lluc Alvarez

Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment.

Max Doblas, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova-Musté, Christopher Frances Batten, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations.

Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC.

Abbas Haghi, Lluc Alvarez, Jordi Fornt, Juan Miguel De Haro Ruiz, Roger Figueras, Max Doblas, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 52nd International Conference on Parallel Processing, 2023

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.

Enrico Reggiani, Alessandro Pappalardo, Max Doblas, Miquel Moretó, Mauro Olivieri, Osman Sabri Unsal, Adrián Cristal

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

RISC-V for Genome Data Analysis: Opportunities and Challenges.

Lorién López-Villellas, Esteve Pineda-Sánchez, Asaf Badouh, Santiago Marco-Sola, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.

Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi.

Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Compiler-Assisted Compaction/Restoration of SIMD Instructions.

Juan M. Cebrian, Thibaud Balem, Adrián Barredo, Marc Casas, Miquel Moretó, Alberto Ros, Alexandra Jimborean

IEEE Trans. Parallel Distributed Syst., 2022

A Security Model for Randomization-based Protected Caches.

Jordi Ribes-González, Oriol Farràs, Carles Hernández, Vatistas Kostalabros, Miquel Moretó

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps.

Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó

IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Accelerating Edit-Distance Sequence Alignment on GPU Using the Wavefront Algorithm.

Quim Aguado-Puig, Santiago Marco-Sola, Juan Carlos Moure, David Castells-Rufas, Lluc Alvarez, Antonio Espinosa, Miquel Moretó

IEEE Access, 2022

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models.

Paul Caheny, Lluc Alvarez, Marc Casas, Miquel Moretó

Proceedings of the SC22: International Conference for High Performance Computing, 2022

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI.

Víctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.

Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.

Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Juan Miguel De Haro Ruiz, Daniel Jiménez-González, Miquel Moretó, Carlos Álvarez, Jesús Labarta, Imen Baili

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

On the use of many-core Marvell ThunderX2 processor for HPC workloads.

Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó

J. Supercomput., 2021

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption.

Cristobal Ortega, Lluc Alvarez, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose, Miquel Moretó

IEEE Trans. Computers, 2021

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip.

Alireza Monemi, Iván Pérez, Neiel Leyva, Enrique Vallejo, Ramón Beivide, Miquel Moretó

Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

PLANAR: a programmable accelerator for near-memory data rearrangement.

Adrián Barredo, Adrià Armejach, Jonathan C. Beard, Miquel Moretó

Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator.

Guillem López-Paradís, Adrià Armejach, Miquel Moretó

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.

Julian Pavon, Iván Vargas Valdivieso, Adrián Barredo, Joan Marimon, Miquel Moretó, Francesc Moll, Osman S. Unsal, Mateo Valero, Adrián Cristal

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem.

Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó, Carles Hernández

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment.

Abbas Haghi, Santiago Marco-Sola, Lluc Alvarez, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors.

David Castells-Rufas, Santiago Marco-Sola, Quim Aguado-Puig, Antonio Espinosa-Morales, Juan Carlos Moure, Lluc Alvarez, Miquel Moretó

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy.

Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the Euro-Par 2021: Parallel Processing, 2021

SafeSU: an Extended Statistics Unit for Multicore Timing Interference.

Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moretó, Carles Hernández, Jaume Abella

Proceedings of the 26th IEEE European Test Symposium, 2021

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors.

Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies.

Adrián Barredo, Juan M. Cebrian, Mateo Valero, Marc Casas, Miquel Moretó

J. Supercomput., 2020

Using Arm's scalable vector extension on stencil codes.

Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó

J. Supercomput., 2020

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86.

Juan M. Cebrian, Adrián Barredo, Helena Caminal, Miquel Moretó, Marc Casas, Mateo Valero

Future Gener. Comput. Syst., 2020

Runtime-guided ECC protection using online estimation of memory vulnerability.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas

Proceedings of the International Conference for High Performance Computing, 2020

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass.

Ivan Perez, Enrique Vallejo, Miquel Moretó, Ramón Beivide

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

RICH: implementing reductions in the cache hierarchy.

Vladimir Dimic, Miquel Moretó, Marc Casas, Jan Ciesko, Mateo Valero

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Modeling and optimizing NUMA effects and prefetching with machine learning.

Isaac Sánchez Barrera, David Black-Schaffer, Marc Casas, Miquel Moretó, Anastasiia Stupnikova, Mihail Popov

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

The DeepHealth Toolkit: A Unified Framework to Boost Biomedical Applications.

Michele Cancilla, Laura Canalini, Federico Bolelli, Stefano Allegretti, Salvador Carrión, Roberto Paredes, Jon Ander Gómez, Simone Leo, Marco Enrico Piras, Luca Pireddu, Asaf Badouh, Santiago Marco-Sola, Lluc Alvarez, Miquel Moretó, Costantino Grana

Proceedings of the 25th International Conference on Pattern Recognition, 2020

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions.

Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA.

Abbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

An Academic RISC-V Silicon Implementation Based on Open-Source Components.

Jaume Abella, Calvin Bulla, Guillem Cabo, Francisco J. Cazorla, Adrián Cristal, Max Doblas, Roger Figueras, Alberto González, Carles Hernández, César Hernández, Víctor Jiménez, Leonidas Kosmidis, Vatistas Kostalabros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Joan Marimon, Ricardo Martínez, Jonnatan Mendoza, Francesc Moll, Miquel Moretó, Julián Pavón, Cristóbal Ramírez, Marco Antonio Ramírez, Carlos Rojas Morales, Antonio Rubio, Abraham Ruiz, Nehir Sönmez, Víctor Soria, Lluís Terés, Osman S. Unsal, Mateo Valero, Iván Vargas Valdivieso, Luis Villa

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

Design trade-offs for emerging HPC processors based on mobile market technology.

Adrià Armejach, Marc Casas, Miquel Moretó

J. Supercomput., 2019

Sampled Simulation of Task-Based Programs.

Thomas Grass, Trevor E. Carlson, Alejandro Rico, Germán Ceballos, Eduard Ayguadé, Marc Casas, Miquel Moretó

IEEE Trans. Computers, 2019

On the maturity of parallel applications for asymmetric multi-core processors.

Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Mateo Valero

J. Parallel Distributed Comput., 2019

The international race towards Exascale in Europe.

Fabrizio Gagliardi, Miquel Moretó, Mauro Olivieri, Mateo Valero

CCF Trans. High Perform. Comput., 2019

Optimizing computation-communication overlap in asynchronous task-based programs: poster.

Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele

Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

On the Benefits of Tasking with OpenMP.

Alejandro Rico, Isaac Sánchez Barrera, José A. Joao, Joshua Randall, Marc Casas, Miquel Moretó

Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip.

Neiel I. Leyva-Santes, Ivan Perez, César-Alejandro Hernández-Calderón, Enrique Vallejo, Miquel Moretó, Ramón Beivide, Marco Antonio Ramírez Salinas, Luis A. Villa-Vargas

Proceedings of the Supercomputing, 2019

Design Space Exploration of Next-Generation HPC Machines.

Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas

Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

A Vulnerability Factor for ECC-protected Memory.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Power efficient job scheduling by predicting the impact of processor manufacturing variability.

Dimitrios Chasapis, Miquel Moretó, Martin Schulz, Barry Rountree, Mateo Valero, Marc Casas

Proceedings of the ACM International Conference on Supercomputing, 2019

Optimizing computation-communication overlap in asynchronous task-based programs.

Emilio Castillo, Nikhil Jain, Marc Casas, Miquel Moretó, Martin Schulz, Ramón Beivide, Mateo Valero, Abhinav Bhatele

Proceedings of the ACM International Conference on Supercomputing, 2019

POSTER: An Optimized Predication Execution for SIMD Extensions.

Adrián Barredo, Juan M. Cebrian, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns.

Adrián Barredo, Jonathan C. Beard, Miquel Moretó

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers.

Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas

IEEE Trans. Parallel Distributed Syst., 2018

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach.

Paul Caheny, Lluc Alvarez, Said Derradji, Mateo Valero, Miquel Moretó, Marc Casas

IEEE Trans. Parallel Distributed Syst., 2018

Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization.

Helena Caminal, Diego Caballero, Juan M. Cebrian, Roger Ferrer, Marc Casas, Miquel Moretó, Xavier Martorell, Mateo Valero

J. Supercomput., 2018

Memory Vulnerability: A Case for Delaying Error Reporting.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas

CoRR, 2018

TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism.

Kallia Chronaki, Marc Casas, Miquel Moretó, Jaume Bosch, Rosa M. Badia

Proceedings of the High Performance Computing - 33rd International Conference, 2018

Runtime-assisted cache coherence deactivation in task parallel programs.

Paul Caheny, Lluc Alvarez, Mateo Valero, Miquel Moretó, Marc Casas

Proceedings of the International Conference for High Performance Computing, 2018

Graph partitioning applied to DAG scheduling to reduce NUMA effects.

Isaac Sánchez Barrera, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.

Calvin Bulla, Lluc Alvarez, Miquel Moretó, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose

Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Data Prefetching on In-order Processors.

Cristobal Ortega, Victor Garcia, Miquel Moretó, Marc Casas, Roxana Rusitoru

Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies.

Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas

Proceedings of the 32nd International Conference on Supercomputing, 2018

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs.

Lluc Alvarez, Marc Casas, Jesús Labarta, Eduard Ayguadé, Mateo Valero, Miquel Moretó

Proceedings of the 32nd International Conference on Supercomputing, 2018

Architectural Support for Task Dependence Management with Flexible Software Scheduling.

Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Stencil codes on a vector length agnostic architecture.

Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

Task Scheduling Techniques for Asymmetric Multi-Core Systems.

Kallia Chronaki, Alejandro Rico, Marc Casas, Miquel Moretó, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero

IEEE Trans. Parallel Distributed Syst., 2017

SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems.

Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero

Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

iQ: An Efficient and Flexible Queue-Based Simulation Framework.

Damian Roca, Daniel Nemirovsky, Marc Casas, Miquel Moretó, Mateo Valero, Mario Nemirovsky

Proceedings of the 25th IEEE International Symposium on Modeling, 2017

ATM: Approximate Task Memoization in the Runtime System.

Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, Gurindar S. Sohi

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

libPRISM: an intelligent adaptation of prefetch and SMT levels.

Cristobal Ortega, Miquel Moretó, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre E. Eichenberger, Pradip Bose

Proceedings of the International Conference on Supercomputing, 2017

Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor.

Ilia Pietri, Sicong Zhuang, Marc Casas, Miquel Moretó, Rizos Sakellariou

Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals.

Vladimir Dimic, Miquel Moretó, Marc Casas, Mateo Valero

Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017

2016

DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems.

Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero

ACM Trans. Design Autom. Electr. Syst., 2016

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.

Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero

IEEE Trans. Computers, 2016

Sensible Energy Accounting with Abstract Metering for Multicore Systems.

Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero

ACM Trans. Archit. Code Optim., 2016

PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite.

Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero

ACM Trans. Archit. Code Optim., 2016

MUSA: a multi-level simulation approach for next-generation HPC machines.

Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó

Proceedings of the International Conference for High Performance Computing, 2016

TaskPoint: Sampled simulation of task-based programs.

Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Eduard Ayguadé

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

CATA: Criticality Aware Task Acceleration for Multicore Processors.

Emilio Castillo, Miquel Moretó, Marc Casas, Lluc Alvarez, Enrique Vallejo, Kallia Chronaki, Rosa M. Badia, José Luis Bosque, Ramón Beivide, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes.

Dimitrios Chasapis, Marc Casas, Miquel Moretó, Martin Schulz, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the 2016 International Conference on Supercomputing, 2016

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware.

Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling.

Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7.

David Prat, Cristobal Ortega, Marc Casas, Miquel Moretó, Mateo Valero

CoRR, 2015

Exploiting asynchrony from exact forward recovery for DUE in iterative solvers.

Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the International Conference for High Performance Computing, 2015

Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads.

Raul Vidal, Marc Casas, Miquel Moretó, Dimitrios Chasapis, Roger Ferrer, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures.

Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Runtime-Aware Architectures.

Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the Euro-Par 2015: Parallel Processing, 2015

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures.

Lluc Alvarez, Miquel Moretó, Marc Casas, Emilio Castillo, Xavier Martorell, Jesús Labarta, Eduard Ayguadé, Mateo Valero

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

Runtime-Aware Architectures: A First Approach.

Mateo Valero, Miquel Moretó, Marc Casas, Eduard Ayguadé, Jesús Labarta

Supercomput. Front. Innov., 2014

Per-task Energy Accounting in Computing Systems.

Qixiao Liu, Víctor Jiménez, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero

IEEE Comput. Archit. Lett., 2014

DReAM: Per-Task DRAM Energy Metering in Multicore Systems.

Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Mateo Valero

Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors.

Thomas Grass, Alejandro Rico, Marc Casas, Miquel Moretó, Alex Ramírez

Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013

Fair CPU time accounting in CMP+SMT processors.

Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Mateo Valero

ACM Trans. Archit. Code Optim., 2013

Hardware support for accurate per-task energy metering in multicore systems.

Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero

ACM Trans. Archit. Code Optim., 2013

Task mapping in rectangular twisted tori.

Cristobal Camarero, Enrique Vallejo, Carmen Martínez, Miquel Moretó, Ramón Beivide

Proceedings of the 2013 Spring Simulation Multiconference, SpringSim '13, 2013

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness.

Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

On the convergence of mainstream and mission-critical markets.

Sylvain Girbal, Miquel Moretó, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Tessellation: refactoring the OS around explicit resource containers with continuous adaptation.

Juan A. Colmenares, Gage Eads, Steven A. Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanovic, John Kubiatowicz

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

CPU Accounting for Multicore Processors.

Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero

IEEE Trans. Computers, 2012

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem.

Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Characterizing thread placement in the IBM POWER7 processor.

Stelios Manousopoulos, Miquel Moretó, Roberto Gioiosa, Nectarios Koziris, Francisco J. Cazorla

Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

Optimal task assignment in multithreaded processors: a statistical approach.

Petar Radojkovic, Vladimir Cakarevic, Miquel Moretó, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011

Dynamic Cache Partitioning Based on the MLP of Cache Misses.

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero

Trans. High Perform. Embed. Archit. Compil., 2011

Simulating Whole Supercomputer Applications.

Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero

IEEE Micro, 2011

2010

Improving cache Behavior in CMP architectures throug cache partitioning techniques.

Miquel Moretó

PhD thesis, 2010

Twisted Torus Topologies for Enhanced Interconnection Networks.

José M. Cámara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas

IEEE Trans. Parallel Distributed Syst., 2010

Adapting cache partitioning algorithms to pseudo-LRU replacement policies.

Kamil Kedzierski, Miquel Moretó, Francisco J. Cazorla, Mateo Valero

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Load balancing using dynamic cache allocation.

Miquel Moretó, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero

Proceedings of the 7th Conference on Computing Frontiers, 2010

2009

FlexDCP: a QoS framework for CMP architectures.

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero

ACM SIGOPS Oper. Syst. Rev., 2009

CPU Accounting in CMP Processors.

Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero

IEEE Comput. Archit. Lett., 2009

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.

Carlos Luque, Miquel Moretó, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero

Proceedings of the PACT 2009, 2009

2008

Modeling Toroidal Networks with the Gaussian Integers.

Carmen Martínez, Ramón Beivide, Esteban Stafford, Miquel Moretó, Ernst M. Gabidulin

IEEE Trans. Computers, 2008

Multicore Resource Management.

Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, James E. Smith

IEEE Micro, 2008

MLP-Aware Dynamic Cache Partitioning.

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero

Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.

Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luis Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee

Proceedings of the Applications of Evolutionary Computing, 2008

Evolutionary system for prediction and optimization of hardware architecture performance.

Pedro Ángel Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Sally A. McKee

Proceedings of the IEEE Congress on Evolutionary Computation, 2008

2007

Explaining Dynamic Cache Partitioning Speed Ups.

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero

IEEE Comput. Archit. Lett., 2007

Online Prediction of Applications Cache Utility.

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Mixed-radix Twisted Torus Interconnection Networks.

José M. Cámara, Miquel Moretó, Enrique Vallejo, Ramón Beivide, José Miguel-Alonso, Carmen Martínez, Javier Navaridas

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors.

Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó

Int. J. Parallel Program., 2006

A Generalization of Perfect Lee Codes over Gaussian Integers.

Carmen Martínez, Miquel Moretó, Ramón Beivide, Ernst M. Gabidulin

Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006