Minyi Lu
Orcid: 0000-0001-7227-3735
According to our database1,
Minyi Lu
authored at least 10 papers
between 2017 and 2021.
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Bibliography
2021
Proceedings of the ICISCAE 2021: 4th International Conference on Information Systems and Computer Aided Education, Dalian, China, September 24, 2021
2020
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.
IEEE Trans. Circuits Syst., 2020
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits, 2020
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020
2018
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access, 2018
Proceedings of the 17th IEEE International Conference On Trust, 2018
A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS.
Proceedings of the 17th IEEE International Conference On Trust, 2018
Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES.
Proceedings of the 17th IEEE International Conference On Trust, 2018
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEICE Electron. Express, 2017