Minxuan Zhou
Orcid: 0000-0002-5523-7270
According to our database1,
Minxuan Zhou
authored at least 30 papers
between 2016 and 2025.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
Fast-OverlaPIM: A Fast Overlap-Driven Mapping Framework for Processing In-Memory Neural Network Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025
2024
ACM Trans. Archit. Code Optim., March, 2024
CoRR, 2024
MathScape: Evaluating MLLMs in multimodal Math Scenarios through a Hierarchical Benchmark.
CoRR, 2024
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Proxima: Near-storage Acceleration for Graph-based Approximate Nearest Neighbor Search in 3D NAND.
CoRR, 2023
CoRR, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
TransPIM: A Memory-based Acceleration via Software-Hardware Co-Design for Transformer.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
PIMProf: An Automated Program Profiler for Processing-in-Memory Offloading Decisions.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021
PIM-DL: Boosting DNN Inference on Digital Processing In-Memory Architectures via Data Layout Optimizations.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021
2020
Temperature-Aware DRAM Cache Management - Relaxing Thermal Constraints in 3-D Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
DUAL: Acceleration of Clustering Algorithms using Digital-based Processing In-Memory.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2016
HV<sup>2</sup>M: A novel approach to boost inter-VM network performance for Xen-based HVMs.
J. Syst. Softw., 2016