Minsu Kim
Affiliations:- Korea Advanced Institute of Science and Technology (KAIST), Department of Electrical Engineering, Daejeon, South Korea
According to our database1,
Minsu Kim
authored at least 28 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
CoRR, 2023
Bootstrapped Training of Score-Conditioned Generator for Offline Design of Biological Sequences.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the International Conference on Machine Learning, 2023
2022
CoRR, 2022
Transformer Network-based Reinforcement Learning Method for Power Distribution Network (PDN) Optimization of High Bandwidth Memory (HBM).
CoRR, 2022
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015
2014
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
24-GOPS 4.5-mm<sup>2</sup> Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC.
IEEE Trans. Neural Networks, 2011
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition.
IEEE J. Solid State Circuits, 2011
2010
An attention controlled multi-core architecture for energy efficient object recognition.
Signal Process. Image Commun., 2010
Familiarity based unified visual attention model for fast and robust object recognition.
Pattern Recognit., 2010
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2010
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.
IEEE J. Solid State Circuits, 2010
A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition.
IEEE Trans. Circuits Syst. Video Technol., 2009
Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining.
IEEE Micro, 2009
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine.
IEEE J. Solid State Circuits, 2009
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008