Minoru Saeki

According to our database, Minoru Saeki authored at least 13 papers between 2004 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack.

Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

Two Operands of Multipliers in Side-Channel Attack.

Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki

IACR Cryptol. ePrint Arch., 2015

2014

On measurable side-channel leaks inside ASIC design primitives.

Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino

J. Cryptogr. Eng., 2014

2011

How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers.

Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Tsutomu Matsumoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques.

Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.

Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style.

Daisuke Suzuki, Minoru Saeki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Security Evaluations of MRSL and DRSL Considering Signal Delays.

Minoru Saeki, Daisuke Suzuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Leakage Analysis of DPA Countermeasures at the Logic Level.

Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.

Daisuke Suzuki, Minoru Saeki

Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005

DPA Leakage Models for CMOS Logic Circuits.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004

Random Switching Logic: A Countermeasure against DPA based on Transition Probability.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

IACR Cryptol. ePrint Arch., 2004