Minkyu Song

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2024
Low-noise Image Sensors with Shifted Pseudo-correlated Multiple Sampling Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Two-step Classification Neuron Circuits for Low-power and High-integration SNN Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
Vizard: Passing Over Profiling-Based Detection by Manipulating Performance Counters.
IEEE Access, 2023

A 0.57 mW@1 FPS In-Column Analog CNN Processor Integrated Into CMOS Image Sensor.
IEEE Access, 2023

Low-Power Single-Slope ADC with a Replica Comparator for Always-on CIS Applications.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022
On-Chip HV Bootstrap Gate Driving for GaN Compatible Power Circuits Operating Above 10 MHz.
IEEE J. Solid State Circuits, 2022

Design of a Feature Extracted CMOS Image Sensor with a Novel Integrator and a Configurable ADC.
Proceedings of the International Conference on Microelectronics, 2022

2021
New Framework for Sequences With Perfect Autocorrelation and Optimal Crosscorrelation.
IEEE Trans. Inf. Theory, 2021

On-CMOS Image Sensor Processing for Lane Detection.
Sensors, 2021

A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and V<sub>SW</sub> Dual-Edge Dead-Time Modulation Techniques.
IEEE J. Solid State Circuits, 2021

33.3 An Automotive-Use 2MHz 100VOUT Flicker-Free Frequency-Modulated GaN-Based Buck-Boost LED Driver Achieving Bootstrap Charge Balancing and 16.8dBμV Radiated EMI Noise Reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 8.9W/mm<sup>2</sup>, 95.4%-Efficiency, CP-Length Tracking Switching Supply Modulator for 5G New Radio mmWave PA Arrays.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits.
Sensors, 2020

2019
A 25-MHz Four-Phase SAW Hysteretic Control DC-DC Converter With 1-Cycle Active Phase Count.
IEEE J. Solid State Circuits, 2019

Correlation of Column Sequences from the Arrays of Sidelnikov Sequences of Different Periods.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Punctured Bent Function Sequences for Watermarked DS-CDMA.
IEEE Commun. Lett., 2019

Hamming correlation properties of the array structure of Sidelnikov sequences.
Des. Codes Cryptogr., 2019

A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

The FM-linear Complexity of M-ary Sidel'nikov Sequences of Period p - 1 = f • M<sup>λ</sup>.
Proceedings of the IEEE International Symposium on Information Theory, 2019

Design of a Hybrid Column Segmented CMOS Image Sensor with an Artificial Intelligence Core and a Novel SRAM Readout Logic.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018
A Construction of Odd Length Generators for Optimal Families of Perfect Sequences.
IEEE Trans. Inf. Theory, 2018

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.
Sensors, 2018

Optimal Families of Perfect Polyphase Sequences from Cubic Polynomials.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Block-Punctured Binary Simplex Codes for Local and Parallel Repair in Distributed Storage Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Design of a Smart Image Sensor with a Current Steering CMOS DAC for High Performance Autofocusing Micro-lens Driver.
Proceedings of the TENCON 2018, 2018

A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous Detector.
Proceedings of the 15th International Conference on Synthesis, 2018

Nano-ampere Current Sensing Technique for OLED Mobile Displays.
Proceedings of the International SoC Design Conference, 2018

2017
A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems.
Sensors, 2017

A construction of optimal generators of odd lengths for perfect sequence families.
Proceedings of the Eighth International Workshop on Signal Design and Its Applications in Communications, 2017

Design of an Asynchronous Detector with Priority Encoding Technique.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine.
Proceedings of the International SoC Design Conference, 2017

Perfect polyphase sequences from cubic polynomials.
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017

2016
16.8 A 3-to-40V 10-to-30MHz automotive-use GaN driver with active BST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiency improvement and 3.4ns constant propagation delay.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design of a configurable bit-resolution CMOS image sensor for the image depth extraction.
Proceedings of the International SoC Design Conference, 2016

Design of LPI signals using optimal families of perfect polyphase sequences.
Proceedings of the 2016 International Symposium on Information Theory and Its Applications, 2016

Correlation properties of sequences from the 2-D array structure of Sidelnikov sequences of different lengths and their union.
Proceedings of the IEEE International Symposium on Information Theory, 2016

A 200-MHz 4-phase fully integrated voltage regulator with local ground sensing dual loop ZDS hysteretic control using 6.5nH package bondwire inductors on 65nm bulk CMOS.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A CMOS Current-Steering D/A Converter With Full-Swing Output Voltage and a Quaternary Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier.
Sensors, 2015

A Full-Swing CMOS Current Steering DAC with an Adaptive Cell and a Quaternary Driver.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A one-shot digital correlated double sampling with a differential difference amplifier for a high speed CMOS image sensor.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A pixel-configurable CMOS image sensor for an intelligent surveillance system.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014
A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors.
Sensors, 2014

Properties and Crosscorrelation of Decimated Sidelnikov Sequences.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A 40-MHz 85.8%-peak-efficiency switching-converter-only dual-phase envelope modulator for 2-W 10-MHz LTE power amplifier.
Proceedings of the Symposium on VLSI Circuits, 2014

A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A CMOS cyclic folding A/D converter with a new compact layout technique.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

An 8-b cascaded folding A/D converter with a new fully differential source follower.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A high dynamic range CMOS image sensor with a digital configurable logarithmic counter.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Combined optimization scheme for degree distributions of LDPC codes.
Proceedings of the 19th Asia-Pacific Conference on Communications, 2013

2012
An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A wide dynamic range CMOS image sensor based on a new gamma correction technique.
Proceedings of the International SoC Design Conference, 2012

Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 65 nm 1.2 V 7-bit 1 GSPS Folding-Interpolation A/D Converter with a Digitally Self-Calibrated Vector Generator.
IEICE Trans. Electron., 2011

2010
A digitally self-calibrated low-noise 7-bit folding A/D converter.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration technique.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit.
IEICE Trans. Electron., 2008

A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Design of a small area and low power CMOS D/A converter based on the Alpha-Power Law MOSFET model.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

A small chip area 12-b 300MS/s Current Steering CMOS D/A converter based on a laminated-step layout technique.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction Technique.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2002
Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique.
VLSI Design, 2002

Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Design of a novel 3.3 V CMOS logarithmic amplifier with a two step linear limiting architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters.
IEEE Trans. Consumer Electron., 2000

Design of novel macro-cells for next generation ASIC cell library.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data converters.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998
Design of a low power 54×54-bit multiplier based on a pass-transistor logic.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL).
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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