Minhan Chen

According to our database, Minhan Chen authored at least 5 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC.

Ping Lu, Minhan Chen, Shaishav Desai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface.

Ping Lu, Bupesh Pandita, Minhan Chen

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications.

Ping Lu, Minhan Chen, Shaishav Desai

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET.

Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

1998

Simulation of Quantum-Dot Structures in Si/SiO₂.

Minhan Chen, Wolfgang Porod

VLSI Design, 1998