Mingshuang Zhang

Orcid: 0009-0000-0357-1421

According to our database1, Mingshuang Zhang authored at least 2 papers in 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells.
IEEE J. Solid State Circuits, December, 2024

21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024


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