Mingoo Seok
Orcid: 0000-0002-9722-0979
According to our database1,
Mingoo Seok
authored at least 169 papers
between 2007 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, August, 2024
A Ten-Level Series-Capacitor 24-to-1-V DC-DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail.
IEEE J. Solid State Circuits, July, 2024
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks.
IEEE J. Solid State Circuits, June, 2024
A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit.
IEEE J. Solid State Circuits, May, 2024
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm.
IEEE J. Solid State Circuits, March, 2024
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, February, 2024
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core.
IEEE J. Solid State Circuits, February, 2024
16.6 PACTOR: A Variation-Tolerant Probing-Attack Detector for a 2.5Gb/s×4-Channel Chip-to-Chip Interface in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
STAR-SRAM: 43.06-TFLOPS/W, 1.89-TFLOPS/mm<sup>2</sup>, 400-Kb/mm<sup>2</sup> Floating-Point SRAM-Based Digital Computing-in-Memory Macro in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector.
IEEE J. Solid State Circuits, 2023
Proceedings of the ACM SIGCOMM 2023 Conference, 2023
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
93.89% Peak Efficiency 24V-to-1V DC-DC Converter with Fast In-Situ Efficiency Tracking and Power-FET Code Roaming.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm<sup>2</sup>, 1005-Kb/mm<sup>2</sup> Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Channel Estimation Using Deep Learning on an FPGA for 5G Millimeter-Wave Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Des. Test, 2022
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE J. Solid State Circuits, 2021
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip.
IEEE J. Solid State Circuits, 2021
0.5-1-V, 90-400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation.
IEEE J. Solid State Circuits, 2021
IEEE Internet Comput., 2021
CoRR, 2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
EQZ-LDO: A Near-Zero EDP Overhead, >10M-Attack-Resilient, Secure Digital LDO featuring Attack-Detection and Detection-Driven Protection for a Correlation-Power-Analysis-Resilient IoT Device.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE J. Solid State Circuits, 2020
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits, 2020
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism.
IEEE J. Solid State Circuits, 2020
Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things.
IEEE J. Solid State Circuits, 2020
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020
A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications.
Int. J. Semantic Comput., 2020
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Design of an Always-On Deep Neural Network-Based 1- $\mu$ W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction.
IEEE J. Solid State Circuits, 2019
MemNet: Memory-Efficiency Guided Neural Architecture Search with Augment-Trim learning.
CoRR, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
FPGA-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory Access.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Master of none acceleration: a comparison of accelerator architectures for analytical query processing.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Ultra-Low-Power Intelligent Acoustic Sensing using Cochlea-Inspired Feature Extraction and DNN Classification.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
<i>In~Situ</i> and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files.
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function.
IEEE J. Solid State Circuits, 2018
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time".
IEEE J. Solid State Circuits, 2018
0.5V-VIN, 165-MA/MM<sup>2</sup> Fully-Integrated Digital LDO Based on Event-Driven Self-Trisuerina Control.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 1μW voice activity detector using analog feature extraction and digital deep neural network.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Better-Than-Worst-Case Design Methodology for a Compact Integrated Switched-Capacitor DC-DC Converter.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
High-Capacity Fingerprint Recognition System based on a Dynamic Memory-Capacity Estimation Technique.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
2017
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Micro, 2017
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities.
IEEE J. Solid State Circuits, 2017
A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability.
CoRR, 2017
Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement.
CoRR, 2017
Compact and voltage-scalable sensor for accurate thermal sensing in dynamic thermal management.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Hotspot monitoring and Temperature Estimation with miniature on-chip temperature sensors.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
A technique to transform 6T-SRAM arrays into robust analog PUF with minimal overhead.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 0.17-mm<sup>2</sup> 3.19-nJ/transform 256-point fast fourier transform core based on spatiotemporally fine-grained active leakage suppression.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Microwatt end-to-End digital neural signal processing systems for motor intention decoding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Extending memory capacity of neural associative memory based on recursive synaptic bit reuse.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
High-Accuracy Compressed Sensing Decoder Based on Adaptive (ℓ<sub>0</sub>, ℓ<sub>1</sub>) Complex Approximate Message Passing: Cross-layer Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Register file circuits and post-deployment framework to monitor aging effects in field.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Compact and Supply-Voltage-Scalable Temperature Sensors for Dense On-Chip Thermal Monitoring.
IEEE J. Solid State Circuits, 2015
Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique.
IEEE J. Solid State Circuits, 2015
A 3.07μm<sup>2</sup>/bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80°C and 0.6 to 1.2V in a 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
14.7 In-situ techniques for in-field sensing of NBTI degradation in an SRAM register file.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space exploration.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space.
Proceedings of the 52nd Annual Design Automation Conference, 2015
A 30.1μm<sup>2</sup>, > ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014
16.4 0.6-to-1.0V 279μm<sup>2</sup>, 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.
IEEE J. Solid State Circuits, 2013
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuits.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
A fine-grained many V<sub>T</sub> design methodology for ultra low voltage operations.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design.
Proceedings of the 48th Design Automation Conference, 2011
2010
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Optimal technology selection for minimizing energy and variability in low voltage applications.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007