Minglun Gao

According to our database¹, Minglun Gao authored at least 26 papers between 2006 and 2019.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2019

SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

2017

SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress).

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Compilers, 2017

2016

OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Exploring stacked main memory architecture for 3D GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A survey of memory architecture for 3D chip multi-processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Calibration method considering second-order error term of timing skew for a novel multi-channel ADC.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Application-level pipelining on Hierarchical NoC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Multi-Gb/s LDPC Code Design and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

An improved scaled DCT architecture.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2009

LDPC decoder design for high rate wireless personal area networks.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2009

Area-efficient reed-solomon decoder design for optical communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Decoder Design for RS-Based LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

VLSI Architecture of Video Post-Processing System for MPEG/H.26X.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

LDPC Decoder Design for IEEE 802.15 Standard.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Scalability Study on Mesh Based Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the PACIIA 2008, 2008

A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A scalable distributed memory architecture for Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System.

[BibT_eX]

[DOI]

Li Li

Yong-Sheng Yin

Minglun Gao

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

On the Implementation of Virtual Array Using Configuration Plane.

[BibT_eX]

[DOI]

Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

2006

An FPGA Implementation of Array LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Minglun Gao

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