Mingjie Lin

Orcid: 0000-0002-8220-962X

According to our database1, Mingjie Lin authored at least 102 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Secure Computing System With Hardware-Efficient Lazy Bonsai Merkle Tree for FPGA-Attached Embedded Memory.
IEEE Trans. Dependable Secur. Comput., 2024

APEX: Ambidextrous Dual-Arm Robotic Manipulation Using Collision-Free Generative Diffusion Models.
CoRR, 2024

RETRO: Reactive Trajectory Optimization for Real-Time Robot Motion Planning in Dynamic Environments.
Proceedings of the IEEE International Conference on Robotics and Automation, 2024

CTR+: A High-Performance Metadata Access Scheme for Secure Embedded Memory in Heterogeneous Computing Systems.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

2023
HMT: A Hardware-centric Hybrid Bonsai Merkle Tree Algorithm for High-performance Authentication.
ACM Trans. Embed. Comput. Syst., July, 2023

FPGA-QHAR: Throughput-Optimized for Quantized Human Action Recognition on The Edge.
CoRR, 2023

DAMON: Dynamic Amorphous Obstacle Navigation using Topological Manifold Learning and Variational Autoencoding.
IROS, 2023

SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

OMT: A Run-time Adaptive Architectural Framework for Bonsai Merkle Tree-Based Secure Authentication with Embedded Heterogeneous Memory.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory Platform.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery.
ACM Trans. Embed. Comput. Syst., 2022

DirectNVM: Hardware-accelerated NVMe SSDs for High-performance Embedded Computing.
ACM Trans. Embed. Comput. Syst., 2022

Intercepting A Flying Target While Avoiding Moving Obstacles: A Unified Control Framework With Deep Manifold Learning.
CoRR, 2022

Reactive Whole-Body Obstacle Avoidance for Collision-Free Human-Robot Interaction with Topological Manifold Learning.
CoRR, 2022

Dynamically Avoiding Amorphous Obstacles with Topological Manifold Learning and Deep Autoencoding.
CoRR, 2022

Learning adaptive control in dynamic environments using reproducing kernel priors with bayesian policy gradients.
Proceedings of the SAC '22: The 37th ACM/SIGAPP Symposium on Applied Computing, Virtual Event, April 25, 2022

Hardware-Efficient Template-Based Deep CNNs Accelerator Design.
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022

Hardware-Efficient Deconvolution-Based GAN for Edge Computing.
Proceedings of the 56th Annual Conference on Information Sciences and Systems, 2022

Non-Parametric Stochastic Policy Gradient with Strategic Retreat for Non-Stationary Environment.
Proceedings of the 18th IEEE International Conference on Automation Science and Engineering, 2022

2021
Safe Locomotion Within Confined Workspace using Deep Reinforcement Learning.
Proceedings of the Fifth IEEE International Conference on Robotic Computing, 2021

HERMES: Hardware-Efficient Speculative Dataflow Architecture for Bonsai Merkle Tree-Based Memory Authentication.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe Storage.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous Computing.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Survivable Robotic Control through Guided Bayesian Policy Search with Deep Reinforcement Learning.
Proceedings of the 17th IEEE International Conference on Automation Science and Engineering, 2021

Design of Scalable Neurotransmitter-mediated Biohybrid Synapse.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Developmentally Synthesizing Earthworm-Like Locomotion Gaits with Bayesian-Augmented Deep Deterministic Policy Gradients (DDPG).
Proceedings of the 16th IEEE International Conference on Automation Science and Engineering, 2020

Survivable Hyper-Redundant Robotic Arm with Bayesian Policy Morphing.
Proceedings of the 16th IEEE International Conference on Automation Science and Engineering, 2020

2019
Survey of Stochastic-Based Computation Paradigms.
IEEE Trans. Emerg. Top. Comput., 2019

Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers.
IEEE Trans. Emerg. Top. Comput., 2019

FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Intelligent Fan System Based on Big Data and Artificial Intelligence.
Proceedings of the 6th International Conference on Systems and Informatics, 2019

Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data Reuse.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Exploiting Irregular Memory Parallelism in Quasi-Stencils through Nonlinear Transformation.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Graph-Morphing: Exploiting Hidden Parallelism of Non-Stencil Computation in High-Level Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Constructive Policy: Reinforcement Learning Approach for Connected Multi-Agent Systems.
Proceedings of the 15th IEEE International Conference on Automation Science and Engineering, 2019

2018
Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

Scalable FPGA Accelerator for Deep Convolutional Neural Networks with Stochastic Streaming.
IEEE Trans. Multi Scale Comput. Syst., 2018

Memory-Efficient Probabilistic 2-D Finite Impulse Response (FIR) Filter.
IEEE Trans. Multi Scale Comput. Syst., 2018

Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm.
IEEE Trans. Computers, 2018

Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing Platform.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

GridGAS: An I/O-Efficient Heterogeneous FPGA+CPU Computing Platform for Very Large-Scale Graph Analytics.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Architecture and Circuit Design of an All-Spintronic FPGA.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Extracting data parallelism in non-stencil kernel computing by optimally coloring folded memory conflict graph.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Sketching Computation with Stochastic Processing Engines.
ACM J. Emerg. Technol. Comput. Syst., 2017

Stochastic-based multi-stage streaming realization of deep convolutional neural network.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Tessellating memory space for parallel access.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Stochastic-Based Deep Convolutional Networks with Reconfigurable Logic Fabric.
IEEE Trans. Multi Scale Comput. Syst., 2016

Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Tessellation-based multi-block memory mapping scheme for high-level synthesis with FPGA.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism.
Microprocess. Microsystems, 2015

Gabor filter polynomial approximation based on a novel evolutionary stochastic technique.
Proceedings of the 34th IEEE Military Communications Conference, 2015

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Neural network-based fuzzy control surface implementation.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Universal Random Number Generation with Field-Programmable Analog Array and Magnetic Tunneling Junction (MTJ) Devices.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Stochastically computing discrete Fourier transform with reconfigurable digital fabric.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Inferring High Quality Co-Travel Networks
CoRR, 2013

Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Extracting memory-level parallelism through reconfigurable hardware traces.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience.
J. Electr. Comput. Eng., 2012

Exploring Many-Core Design Templates for FPGAs and ASICs.
Int. J. Reconfigurable Comput., 2012

Exploiting Memory-Level Parallelism in Reconfigurable Accelerators.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
Discriminatively Fortified Computing with Reconfigurable Digital Fabric.
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

Using many-core architectural templates for FPGA-based computing (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Exploring FPGA Routing Architecture Stochastically.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

MARC: A Many-Core Approach to Reconfigurable Computing.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Scalable architecture for programmable quantum gate array (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

High-throughput bayesian computing machine with reconfigurable hardware.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
A Low-Power Field-Programmable Gate Array Routing Fabric.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
A low-power monolithically stacked 3D-TCAM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

TORCH: a design tool for routing channel segmentation in FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

The amorphous FPGA architecture.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007
Performance Benefits of Monolithically Stacked 3-D FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Collaborative Routing Architecture for FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A routing fabric for monolithically stacked 3D-FPGA.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006
Power-efficient rate scheduling in wireless links using computational geometric algorithms.
Proceedings of the International Conference on Wireless Communications and Mobile Computing, 2006

Performance benefits of monolithically stacked 3D-FPGA.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
The throughput of a buffered crossbar switch.
IEEE Commun. Lett., 2005

k-Server Optimal Task Scheduling Problem with Convex Cost Function.
Proceedings of the 3rd International Symposium on Modeling and Optimization in Mobile, 2005


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