Ming Ming Wong
Orcid: 0000-0002-6420-1202
According to our database1,
Ming Ming Wong
authored at least 34 papers
between 2010 and 2024.
Collaborative distances:
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Bibliography
2024
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
2023
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140].
Neurocomputing, 2022
Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency.
Neurocomputing, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021
2020
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Future Gener. Comput. Syst., 2018
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Construction of a Low Multiplicative Complexity GF (2<sup>4</sup>) Inversion Circuit for Compact AES S-Box.
Proceedings of the TENCON 2018, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
2014
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014
Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014
2012
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the Network and Parallel Computing, 9th IFIP International Conference, 2012
Proceedings of the 20th European Signal Processing Conference, 2012
2011
Composite field GF(((2<sup>2</sup>)<sup>2</sup>)<sup>2</sup>) advanced encryption standard (AES) S-box with algebraic normal form representation in the subfield inversion.
IET Circuits Devices Syst., 2011
2010
Comput. Electr. Eng., 2010
A new common subexpression elimination algorithm with application in composite field AES S-box.
Proceedings of the 10th International Conference on Information Sciences, 2010