Ming Liu

Orcid: 0000-0002-0937-7547

Affiliations:
  • Chinese Academy Sciences, Institute of Microelectronics, Beijing, China


According to our database1, Ming Liu authored at least 74 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2024
SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros.
IEEE J. Solid State Circuits, November, 2024

Hardware Implementation of Next Generation Reservoir Computing with RRAM-Based Hybrid Digital-Analog System.
Adv. Intell. Syst., October, 2024

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.
IEEE J. Solid State Circuits, August, 2024

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.
IEEE J. Solid State Circuits, May, 2024

A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
IEEE J. Solid State Circuits, January, 2024

Binary-Stochasticity-Enabled Highly Efficient Neuromorphic Deep Learning Achieves Better-than-Software Accuracy.
Adv. Intell. Syst., January, 2024

Dynamic neural network with memristive CIM and CAM for 2D and 3D vision.
CoRR, 2024

Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver.
CoRR, 2024

Efficient and accurate neural field reconstruction using resistive memory.
CoRR, 2024

Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model.
CoRR, 2024

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

High-efficient and Comprehensive Modeling of MFIM Ferroelectric Tunnel Junctions for Non-volatile/Volatile Applications.
Proceedings of the IEEE International Memory Workshop, 2024

A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow.
IEEE Trans. Circuits Syst. Video Technol., December, 2023

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier.
IEEE J. Solid State Circuits, October, 2023

Echo state graph neural networks with analogue random resistive memory arrays.
Nat. Mac. Intell., February, 2023

Random resistive memory-based deep extreme point learning machine for unified visual processing.
CoRR, 2023

Pruning random resistive memory for optimizing analogue AI.
CoRR, 2023

Resistive memory-based zero-shot liquid state machine for multimodal event data learning.
CoRR, 2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 9Mb HZO-Based Embedded FeRAM with 10<sup>12</sup>-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.
IEEE J. Solid State Circuits, 2022

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm<sup>2</sup>) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A low-power twiddle factor addressing architecture for split-radix FFT processor.
Microelectron. J., 2021

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.
IEEE J. Solid State Circuits, 2021

Echo state graph neural networks with analogue random resistor arrays.
CoRR, 2021

Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design.
Sci. China Inf. Sci., 2021

Investigation of weight updating modes on oxide-based resistive switching memory synapse towards neuromorphic computing applications.
Sci. China Inf. Sci., 2021

24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m<sup>2</sup> Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

14.6 A 76-to-81GHz 2×8 FMCW MIMO Radar Transceiver with Fast Chirp Generation and Multi-Feed Antenna-in-Package Array.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique.
IEEE J. Solid State Circuits, 2020

A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm<sup>2</sup> using Sneaking Current Suppression and Compensation Techniques.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique.
IEICE Electron. Express, 2019

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond.
CoRR, 2019

Total ionizing dose effects on graphene-based charge-trapping memory.
Sci. China Inf. Sci., 2019

A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Resistive Switching Devices: Mechanism, Performance and Integration.
Proceedings of the Handbook of Memristor Networks., 2019

2018
Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Total ionizing dose effects and annealing behaviors of HfO<sub>2</sub>-based MOS capacitor.
Sci. China Inf. Sci., 2017

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Study of total ionizing dose induced read bit errors in magneto-resistive random access memory.
Microelectron. Reliab., 2016

A 25Gb/s low-noise optical receiver in 0.13 μm SiGe BiCMOS.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Impact of P/E cycling on read current fluctuation of NOR Flash memory cell: A microscopic perspective based on low frequency noise analysis.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2011
FPGA Based on Integration of CMOS and RRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2011

3D Integration of CMOL Structures for FPGA Applications.
IEEE Trans. Computers, 2011

2010
Formation and annihilation of Cu conductive filament in the nonpolar resistive switching Cu/ZrO2: Cu/Pt ReRAM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A low power single ended input differential output low noise amplifier for L1/L2 band.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

FPGA based on integration of carbon nanorelays and CMOS devices.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

2008
FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications.
Proceedings of the Nano-Net - Third International ICST Conference, 2008

rFGA: CMOS-nano hybrid FPGA using RRAM components.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Analyzing mixed carbon nanotube bundles: A current density study.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Fault Tolerance Circuit for AM-OLED.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Modeling and simulation development of electron beam resist based on cellular automata.
Microelectron. J., 2006

Hybrid Nanoelectronics: Future of Computer Technology.
J. Comput. Sci. Technol., 2006


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