Ming-Hwa Sheu
Orcid: 0000-0002-8417-474X
According to our database1,
Ming-Hwa Sheu
authored at least 106 papers
between 1993 and 2024.
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Bibliography
2024
High Precision, Low Complexity, and Fast Calculation Based on Hybrid Recursive DFT and FFT Algorithms for Electrochemical Impedance Spectroscopy System.
IEEE Trans. Instrum. Meas., 2024
Proceedings of the 21st International SoC Design Conference, 2024
2023
IEEE Trans. Instrum. Meas., 2023
Improvement of Human Pose Estimation and Processing With the Intensive Feature Consistency Network.
IEEE Access, 2023
Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network.
Proceedings of the 20th International SoC Design Conference, 2023
Unique Feature Extraction and Consistency Network for Skeleton Body Keypoints Configuration and Enhancement.
Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023
Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023
2022
FHI-Unet: Faster Heterogeneous Images Semantic Segmentation Design and Edge AI Implementation for Visible and Thermal Images Processing.
IEEE Access, 2022
FIBS-Unet: Feature Integration and Block Smoothing Network for Single Image Dehazing.
IEEE Access, 2022
IEEE Access, 2022
Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients.
IEEE Access, 2022
Integration Design of Portable ECG Signal Acquisition With Deep-Learning Based Electrode Motion Artifact Removal on an Embedded System.
IEEE Access, 2022
2021
A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.
Sensors, 2021
FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting.
Sensors, 2021
Microelectron. J., 2021
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Software and Hardware Integration System Design with Fruit Identification for Smart Electronic Scale Applications.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2020
IEEE Access, 2020
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
2019
A Fast Non-Overlapping Multi-Camera People Re-Identification Algorithm and Tracking Based on Visual Channel Model.
IEICE Trans. Inf. Syst., 2019
IEICE Trans. Electron., 2019
Proceedings of the Eleventh International Conference on Ubiquitous and Future Networks, 2019
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
2018
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017
High-performance reverse converter design for the new four-moduli Set {2<sup>2n</sup>, 2<sup>n</sup>+1, 2<sup>n/2</sup>+1, 2<sup>n/2</sup>-1}.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017
2016
New adaptable three-moduli set {2<i><sup>n</sup></i><sup>+</sup><i><sup>k</sup></i>, 2<i><sup>n</sup></i> - 1, 2<i><sup>n</sup></i><sup>-1</sup> - 1} for residue number system-based finite impulse response implementation.
IEICE Electron. Express, 2016
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
2014
High Dynamic Range Image Based on Block-Based Edge Strength for Embedded System Design.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014
Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014
2013
Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2<sup><i>n</i> + <i>k</i></sup>, 2<sup><i>n</i></sup> + 1, 2<sup><i>n</i></sup> - 1, 2<sup>2<i>n</i></sup> + 1}.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the Ninth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2013
Proceedings of the Ninth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2013
2012
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms.
IEEE Embed. Syst. Lett., 2012
A hybrid pixel-based background model for image foreground object detection in complex sence.
Proceedings of the 35th International Conference on Telecommunications and Signal Processing, 2012
A robust background modeling and foreground object detection using color component analysis.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012
Fast image moving object segmentation based on block texture for embedded system implementation.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2012
2011
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011
2010
Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction.
IEEE Trans. Circuits Syst. Video Technol., 2010
J. Inf. Sci. Eng., 2010
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection.
Proceedings of the Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), 2010
Proceedings of the Fifth International Conference on Frontier of Computer Science and Technology, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2<sup>p+k</sup>, 2<sup>p</sup>+1, 2<sup>p</sup>-1, 2<sup>2p</sup>+1).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009
2008
VLSI Design of Diminished-One Modulo 2<sup>n</sup>+1 Adder Using Circular Carry Selection.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
High-performance very large scale integration architecture design for various-ratio image scaling.
J. Electronic Imaging, 2008
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2<sup><i>n</i></sup>, 2<sup><i>n</i>+1</sup> - 1, 2<sup><i>n</i></sup> - 1).
IEICE Trans. Inf. Syst., 2008
Area-Time Efficient Modulo 2<sup><i>n</i></sup> - 1 Adder Design Using Hybrid Carry Selection.
IEICE Trans. Inf. Syst., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Electron. Express, 2008
The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing.
Proceedings of the International Conference on Embedded Software and Systems, 2008
Real-time FPGA architecture of extended linear convolution for digital image scaling.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2<sup>n</sup>, 2<sup>n+1</sup>-1, 2<sup>n</sup>-1).
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007
2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the Advances in Multimedia Information Processing, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
An efficient VLSI design for a residue to binary converter for general balance moduli (2<sup>n</sup>-3, 2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>n</sup>+3).
IEEE Trans. Circuits Syst. II Express Briefs, 2004
2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
IEEE J. Solid State Circuits, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
An efficient approach for in-place scheduling of path metric update in Viterbi decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1993
An Expandable Chip Desing for Gray-scale Morphological Operations.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A High Throughput-Rate Architecture for 8*8 2-D DCT.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993