Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-Axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 μC/cm<sup>2</sup> with Endurance > 4E12.

[BibT_eX]

[DOI]

Zefu Zhao

Yu-Rui Chen

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Reliability Assessment for an In-3D-NAND Approximate Searching Solution.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2024

3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2024

2023

SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2023

2022

In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2022

2017

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

2016

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Ming-Hsiu Lee

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...