Ming-Hsien Tu
According to our database1,
Ming-Hsien Tu
authored at least 18 papers
between 2008 and 2017.
Collaborative distances:
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Bibliography
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line.
Microelectron. J., 2016
2015
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits, 2012
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
2011
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design.
IEICE Trans. Electron., 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008