Ming-e Jing

According to our database¹, Ming-e Jing authored at least 43 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

A High-Throughput and Memory-Efficient Deblocking Filter Hardware Architecture for VVC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., December, 2024

PixRevive: Latent Feature Diffusion Model for Compressed Video Quality Enhancement.

[BibT_eX]

[DOI]

Sensors, March, 2024

Unicorn: Unified Neural Image Compression with One Number Reconstruction.

[BibT_eX]

[DOI]

CoRR, 2024

SFFTNet: Sparse Feature Fusion Transformer Network for Image Deblurring.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

LCCStyle: Arbitrary Style Transfer With Low Computational Complexity.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2023

An Efficient Bundle Adjustment Approach for Stereo Visual Odometry with Pose Consensus.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2023

Performance Error Evaluation of gem5 Simulator for ARM Server.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Tear the Image Into Strips for Style Transfer.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2022

2021

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Fast Style Transfer with High Shape Retention.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Mutli-level Regression Anchor-free Object Detection.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Small Object Detection in Aerial Images.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Arbitrary Style Transfer via Learning to Paint in the Feature Domain.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

Knowledge Distillation for U-Net Based Image Denoising.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Fast QTMT Partition Decision Strategy for VVC Intra Prediction.

[BibT_eX]

[DOI]

IEEE Access, 2020

Directly Obtaining Matching Points without Keypoints for Image Stitching.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Single Image Dehazing using a Novel Histogram Tranformation Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Hardware Friendly Haze Removal Method and Its Implementation.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

CS-MCNet: A Video Compressive Sensing Reconstruction Network with Interpretable Motion Compensation.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ACCV 2020 - 15th Asian Conference on Computer Vision, Kyoto, Japan, November 30, 2020

2019

Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Visual Communications and Image Processing, 2019

A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Very Deep Residual Network for Image Matting.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

Enhanced Recursive Residual Network for Single Image Super-Resolution.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

An Automatic Task Partition Method for Multi-core System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F<sup>2</sup> and K-means Clustering for Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Time-Division-Multiplexer based routing algorithm for NoC system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Implementation and optimization of 3780-point FFT on multi-core system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Efficient implementation of 3780-point FFT on a 16-core processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Task-binding based branch-and-bound algorithm for NoC mapping.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Analog layout retargeting with geometric programming and constrains symbolization method.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A method of quadratic programming for mapping on NoC architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

A Folding Strategy for SAT solvers based on Shannon's expansion theorem.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2007

A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Solving SAT problem by heuristic polarity decision-making algorithm.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2007

2005

Efficient parametric yield optimization of VLSI circuit by uniform design sampling method.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2005

Ming-e Jing

Timeline

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On csauthors.net:

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