Ming-Chiuan Su

According to our database, Ming-Chiuan Su authored at least 5 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.

Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou

IEICE Trans. Electron., 2016

2015

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs.

Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen

IEEE Trans. Very Large Scale Integr. Syst., 2015

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression.

Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2013

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression.

Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

Digitally-controlled cell-based oscillator with multi-phase differential outputs.

Ming-Chiuan Su, Shyh-Jye Jou

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011