Mingche Lai
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface.
Microelectron. J., 2024
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.
Microelectron. J., 2024
IEICE Electron. Express, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
Microelectron. J., October, 2023
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023
2022
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J., 2022
Hierarchical photoelectric hybrid packet switching network for high-performance computing.
JOCN, 2022
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access, 2022
Proceedings of the Network and Parallel Computing, 2022
In-Band Management Framework and Performance Evaluation for Interconnect Network in the TianHe Exascale Prototype System.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
2021
Proceedings of the 17th IFIP/IEEE International Symposium on Integrated Network Management, 2021
2020
A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management.
Neurocomputing, 2020
Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
2019
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019
PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2019
2018
Frontiers Inf. Technol. Electron. Eng., 2018
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing.
ACM J. Emerg. Technol. Comput. Syst., 2018
Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings.
J. Comput. Networks Commun., 2018
2016
A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS.
IEICE Trans. Commun., 2016
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016
2015
A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015
2014
IEEE Trans. Computers, 2014
2013
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP.
Parallel Comput., 2013
An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network.
Sci. China Inf. Sci., 2013
Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013
2011
Microprocess. Microsystems, 2011
Two-level tries: A general acceleration structure for parallel routing table accesses.
J. Commun. Networks, 2011
Sci. China Inf. Sci., 2011
Proceedings of the Sixth Chinagrid Annual Conference, ChinaGrid 2011, Dalian, Liaoning, 2011
2010
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains.
IET Comput. Digit. Tech., 2010
2009
Proceedings of the International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, 2009
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009
An accurate and efficient performance analysis approach based on queuing model for network on chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
Proceedings of the 9th International Conference for Young Computer Scientists, 2008
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 2008
Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain.
Proceedings of the Second International Conference on Complex, 2008
Proceedings of the Second International Conference on Complex, 2008
Proceedings of the Second International Conference on Complex, 2008
2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE 2007), 2007
Proceedings of the Multimedia Content Analysis and Mining, International Workshop, 2007
2006
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
2005
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005
2004
Proceedings of the Embedded Software and Systems, First International Conference, 2004