Mineo Kaneko
Orcid: 0009-0008-5072-111X
According to our database1,
Mineo Kaneko
authored at least 94 papers
between 1993 and 2024.
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Bibliography
2024
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
Energy Balancing of Power System Considering Periodic Behavioral Pattern of Renewable Energy Sources and Demands.
IEEE Access, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Optimal Location and Sizing of Renewable Distributed Generators for Improving Robust Voltage Stability Against Uncontrollable Reactive Compensation.
IEEE Access, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
2020
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A random access analog memory with master-slave structure for implementing hexadecimal logic.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Mixed error correction scheme and its design optimization for soft-error tolerant datapaths.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism.
ACM Trans. Design Autom. Electr. Syst., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Proceedings of the IEEE PES Innovative Smart Grid Technologies Conference, 2014
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract].
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
2013
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
An efficient approach for designing and minimizing reversible programmable logic arrays.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Early planning for RT-level delay insertion during clock skew-aware register binding.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
A complete framework of simultaneous functional unit and register binding with skew scheduling.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Ordered coloring-based resource binding for datapaths with improved skew-adjustability.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 26th International Conference on Computer Design, 2008
2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
3D scheduling based on code space exploration for dynamically reconfigurable systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Extended dimensional threshold filtering-a bridge between FIR filter and median type filter.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000
An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
1999
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
1997
Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1994
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993