Minchang Cho
Orcid: 0000-0002-4044-0276
According to our database1,
Minchang Cho
authored at least 9 papers
between 2016 and 2022.
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Bibliography
2022
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End.
IEEE J. Solid State Circuits, 2022
2021
A 192 nW 0.02 Hz High Pass Corner Acoustic Analog Front-End with Automatic Saturation Detection and Recovery.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
AµProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
An Acoustic Signal Processing Chip With 142-nW Voice Activity Detection Using Mixer-Based Sequential Frequency Scanning and Neural Network Classification.
IEEE J. Solid State Circuits, 2019
A 142nW Voice and Acoustic Activity Detection Chip for mm-Scale Sensor Nodes Using Time-Interleaved Mixer-Based Frequency Scanning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
IoT<sup>2</sup> - the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2017
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016