Minas Dasygenis

Proceedings of the 4th South-East Europe Design Automation, 2019

HLS Accelerated Noise Reduction Approach Using Image Stacking on Xilinx PYNQ.

[BibT_eX]

[DOI]

Dimitris Tsiktsiris

Dimitris Ziouzios

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor.

[BibT_eX]

[DOI]

Argirios Sideris

Theodora Sanida

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Autonomous Obstacle Avoidance Vehicle Using LIDAR and an Embedded System.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Multi-Robot Coverage Path Planning in 3-Dimensional Environments.

[BibT_eX]

[DOI]

Nikolaos Baras

Nikolaos Ploskas

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

2018

Methods for Parallelizing Constraint Propagation through the Use of Strong Local Consistencies.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 2018

Design and development of an android application with supportive website in order to create a travel guide for western macedonia.

[BibT_eX]

[DOI]

Eleni Regkou

Proceedings of the 22nd Pan-Hellenic Conference on Informatics, 2018

Web information system for natural gas technicians dealing with malfunctions management: iGasService.

[BibT_eX]

[DOI]

Iliana Potsika

Proceedings of the 22nd Pan-Hellenic Conference on Informatics, 2018

A portable image processing accelerator using FPGA.

[BibT_eX]

[DOI]

Dimitris Tsiktsiris

Dimitris Ziouzios

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Design and implementation of an open-source infrastructure and an intelligent thermostat.

[BibT_eX]

[DOI]

Anastasios Loumpas

Georgios Panaras

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017

Exploiting the Pruning Power of Strong Local Consistencies Through Parallelization.

[BibT_eX]

[DOI]

CoRR, 2017

Automating the generation of hardware accelerators from custom arithmetic functions.

[BibT_eX]

[DOI]

Proceedings of the 21st Pan-Hellenic Conference on Informatics, 2017

Template matching of a coarse grain reconfigurable architecture datapath using constraint programming.

[BibT_eX]

[DOI]

Paris-Alexandros Karypidis

Thanasis Karpouzis

Konstantinos Stergiou

Proceedings of the 21st Pan-Hellenic Conference on Informatics, 2017

Real time detection of suspicious objects in public areas using computer vision.

[BibT_eX]

[DOI]

Moukoulis Achilleas

Diamantidou Eleni

Proceedings of the 21st Pan-Hellenic Conference on Informatics, 2017

Parallelization and energy evaluation of interframe compression technique for video images - QSDPCM.

[BibT_eX]

[DOI]

Panagiotis N. Smyrlis

Dimosthenis C. Tsouros

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Realization of a hardware generator for the sum of absolute difference component.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Implementation of a motion estimation hardware accelerator on Zynq SoC.

[BibT_eX]

[DOI]

Thomas Makryniotis

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2016

Using Parallelization to Efficiently Exploit the Pruning Power of Strong Local Consistencies.

[BibT_eX]

[DOI]

Proceedings of the 9th Hellenic Conference on Artificial Intelligence, 2016

Rapid Implementation of Embedded Systems using Xilinx Zynq Platform.

[BibT_eX]

[DOI]

Thomas Makryniotis

Proceedings of the SouthEast European Design Automation, 2016

Leveraging Parallelization Opportunities by an Online CAD Tool.

[BibT_eX]

[DOI]

Orestis Gounalakis

Anastasios Lytos

Proceedings of the SouthEast European Design Automation, 2016

Development of a Hybrid Defensive Embedded System with Face Recognition.

[BibT_eX]

[DOI]

Maria Tsourma

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

An Online Tool to Design Highly Parametrized Optimized Encoders and Decoders.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

An Efficient Scalable Parallelized Version of the Mondrian Algorithm.

[BibT_eX]

[DOI]

John Christoforidis

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015

Generation and Validation of Custom Multiplication IP Blocks from the Web.

[BibT_eX]

[DOI]

CoRR, 2015

A CAD tool for custom magnitude comparators.

[BibT_eX]

[DOI]

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

A networking EDA tool for multi-vector multiplication IP circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A generic moduli selection algorithm for the Residue Number System.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Designing optimized forward residue number systems IP blocks converters from a network interface.

[BibT_eX]

[DOI]

Giannis Petrousov

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

Design, Implementation and Verification of a Customizing IP Soft Core With FPU Support.

[BibT_eX]

[DOI]

Angelos Ntasios

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

Evaluating modern parallelization techniques on block matching algorithms.

[BibT_eX]

[DOI]

Panagiotis D. Michailidis

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

A unique network EDA tool to create optimized ad hoc binary to residue number system converters.

[BibT_eX]

[DOI]

Giannis Petrousov

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

A distributed VHDL compiler and simulator accessible from the web.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Building Portfolios for Parallel Constraint Solving by Varying the Local Consistency Applied.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Tools with Artificial Intelligence, 2014

Generation and validation of multioperand carry save adders from the web.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2008

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2006

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Σχεδιασμός πολύπλοκων ενσωματωμένων συστημάτων με χαμηλή κατανάλωση ισχύος και υψηλές επιδόσεις

[BibT_eX]

[DOI]

PhD thesis, 2005

A Modified Spiral Search Algorithm and its Embedded Hardware Implementation.

[BibT_eX]

Proceedings of the International Enformatika Conference, 2005

Improving the Memory Bandwidth Utilization Using Loop Transformations.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

A modified spiral search motion estimation algorithm and its embedded system implementation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

2003

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.

[BibT_eX]

[DOI]

Real Time Imaging, 2003

2002

Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

A novel division algorithm for parallel and sequential processing.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A full adder based methodology for scaling operation in residue number system.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

A CAD tool for architecture level exploration and automatic generation of RNS converters.

[BibT_eX]

[DOI]

D. J. Soudris

Spyridoula K. Vasilopoulou

Adonios Thanailakis

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power, performance and area exploration of block matching algorithms mapped on programmable processors.

[BibT_eX]

[DOI]

Constantinos E. Goutis

Proceedings of the 2001 International Conference on Image Processing, 2001

Data and instruction memory exploration of embedded systems for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

2000

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.

[BibT_eX]

[DOI]

Constantinos E. Goutis

Adonios Thanailakis

Proceedings of the Integrated Circuit Design, 2000

Designing RNS and QRNS full adder based converters.

[BibT_eX]

[DOI]

D. J. Soudris