Min Zhao

According to our database, Min Zhao authored at least 26 papers between 1998 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.

Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Power Grid Analysis and Optimization Using Algebraic Multigrid.

Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.

Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.

Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A novel technique for incremental analysis of on-chip power distribution networks.

Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.

Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan

Proceedings of the 44th Design Automation Conference, 2007

2006

Optimal placement of power-supply pads and pins.

Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Fast decap allocation based on algebraic multigrid.

Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.

Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu

Proceedings of the 43rd Design Automation Conference, 2006

2005

Timing driven track routing considering coupling capacitance.

Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Exploiting level sensitive latches in wire pipelining.

V. Seth, Min Zhao, Jiang Hu

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Layer assignment for crosstalk risk minimization.

Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Fast on-chip inductance simulation using a precorrected-FFT method.

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Statistical delay computation considering spatial correlations.

Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Technology mapping algorithms for domino logic.

Min Zhao, Sachin S. Sapatnekar

ACM Trans. Design Autom. Electr. Syst., 2002

Hierarchical analysis of power distribution networks.

Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Worst case clock skew under power supply variations.

Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A precorrected-FFT method for simulating on-chip inductance.

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

A New Structural Pattern Matching Algorithm for Technology Mapping.

Min Zhao, Sachin S. Sapatnekar

Proceedings of the 38th Design Automation Conference, 2001

Inductance 101: Analysis and Design Issues.

Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao

Proceedings of the 38th Design Automation Conference, 2001

2000

Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.

Min Zhao, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic.

Min Zhao, Sachin S. Sapatnekar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Hierarchical analysis of power distribution networks.

Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw

Proceedings of the 37th Conference on Design Automation, 2000

1999

Timing-driven partitioning for two-phase domino and mixed static/domino implementations.

Min Zhao, Sachin S. Sapatnekar

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Technology mapping for domino logic.

Min Zhao, Sachin S. Sapatnekar

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998