Min-Jer Wang
According to our database1,
Min-Jer Wang
authored at least 28 papers
between 2008 and 2020.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE International Test Conference in Asia, 2020
Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill.
Proceedings of the IEEE International Test Conference in Asia, 2020
2019
Proceedings of the IEEE International Test Conference, 2019
2017
IEEE Trans. Computers, 2017
IEEE Des. Test, 2017
Proceedings of the International Test Conference in Asia, 2017
Proceedings of the International Test Conference in Asia, 2017
2016
IEEE Trans. Computers, 2016
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.
IEEE Des. Test, 2016
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits, 2014
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS<sup>TM</sup>/3D ICs.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 International Test Conference, 2014
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch.
Proceedings of the 2013 IEEE International Test Conference, 2013
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.
Proceedings of the 2013 IEEE International Test Conference, 2013
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm<sup>2</sup> per MB.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A memory yield improvement scheme combining built-in self-repair and error correction codes.
Proceedings of the 2012 IEEE International Test Conference, 2012
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008