Milovan Blagojevic
According to our database1,
Milovan Blagojevic
authored at least 10 papers
between 2014 and 2017.
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Collaborative distances:
Timeline
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2017
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Bibliography
2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017
2016
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
2014
27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014