Milos Stanisavljevic
According to our database1,
Milos Stanisavljevic
authored at least 29 papers
between 2005 and 2024.
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Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
HERMES-Core - A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.
IEEE J. Solid State Circuits, 2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.
Frontiers Comput. Neurosci., 2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2019, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology.
Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018
2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
2015
Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2010
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Selective redundancy-based design techniques for the minimization of local delay variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Int. J. Nanotechnol. Mol. Comput., 2009
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR).
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
An Enhanced Service Provider Communication Interface with Client Prioritization - Case Study on Fast-food Chain Restaurants.
Proceedings of the ICE-B 2008, 2008
2007
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.
Proceedings of the International Joint Conference on Neural Networks, 2006
2005
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005