Milos Panic

According to our database, Milos Panic authored at least 13 papers between 2013 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A time-predictable many-core processor design for critical real-time embedded systems.

Milos Panic

PhD thesis, 2018

2017

Adapting TDMA arbitration for measurement-based probabilistic timing analysis.

Milos Panic, Jaume Abella, Eduardo Quiñones, Carles Hernández, Theo Ungerer, Francisco J. Cazorla

Microprocess. Microsystems, 2017

Evaluation of fine-grained parallelism in AUTOSAR applications.

Alexander Stegmeier, Sebastian Kehr, Dave George, Christian Bradatsch, Milos Panic, Bert Bodekker, Theo Ungerer

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore.

Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel G. Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernández, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka

ACM Trans. Embed. Comput. Syst., 2016

Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems.

Milos Panic, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Improving performance guarantees in wormhole mesh NoC designs.

Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Supertask: Maximizing runnable-level parallelism in AUTOSAR applications.

Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schäfer

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores.

Milos Panic, Eduardo Quiñones, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enabling TDMA Arbitration in the Context of MBPTA.

Milos Panic, Jaume Abella, Carles Hernández, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Parallel many-core avionics systems.

Milos Panic, Eduardo Quiñones, Pavel G. Zaykov, Carles Hernández, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2014 International Conference on Embedded Software, 2014

RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores.

Milos Panic, Sebastian Kehr, Eduardo Quiñones, Bert Böddeker, Jaume Abella, Francisco J. Cazorla

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

On-chip ring network designs for hard-real time systems.

Milos Panic, Germán Rodríguez, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla

Proceedings of the 21st International Conference on Real-Time Networks and Systems, 2013

parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability.

Theo Ungerer, Christian Bradatsch, Mike Gerdes, Florian Kluge, Ralf Jahr, Jörg Mische, João Fernandes, Pavel G. Zaykov, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Ian Broster, Nick Lay, David George, Eduardo Quiñones, Milos Panic, Jaume Abella, Francisco J. Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013