Milos Krstic

Orcid: 0000-0003-0267-0203

Affiliations:
  • Innovations for High Performance Microelectronics (IHP), Frankfurt (Oder), Germany
  • University of Potsdam, Germany
  • Brandenburg University of Technology, Cottbus, Germany (PhD 2006)


According to our database1, Milos Krstic authored at least 185 papers between 2003 and 2024.

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Bibliography

2024
An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Test Cost Reduction for VLSI Adaptive Test With K-Nearest Neighbor Classification Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

Design and analysis of an adaptive radiation resilient RRAM subsystem for processing systems in satellites.
Des. Autom. Embed. Syst., June, 2024

Machine Learning Methodologies to Predict the Results of Simulation-Based Fault Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

On the Influence of the Laser Illumination on the Logic Cells Current Consumption.
CoRR, 2024

FPGA Implementation of a Fault-Tolerant Fused and Branched CNN Accelerator With Reconfigurable Capabilities.
IEEE Access, 2024

Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

On the Influence of Cell Libraries and Other Parameters to SCA Resistance of Crypto IP Cores.
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Silicon Lifecycle Management Based on On-Chip Cross-Layer Sensing and Analytics for Space Applications.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Aging and Soft Error Resilience in Reconfigurable CNN Accelerators Employing a Multi-Purpose On-Chip Sensor.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Space Radiation Flux Driven Fault Injection for Evaluating Dynamic Mitigation Strategies.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Simulation-Based Analysis and Modeling of Generated Single Event Transient Pulse Width.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

A Holistic Approach for Characterization of SET Effects in a Standard Digital Cell Library.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

From Device to Application - Integrating RRAM Accelerator Blocks into Large AI Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Area-Efficient Digital Design Using RRAM-CMOS Standard Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Self-Aware Reliable and Reconfigurable Computing Systems - An Overview.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Enhancing the WLAN OFDM-PHY by OTFS Precoding.
Proceedings of the Joint European Conference on Networks and Communications & 6G Summit, 2024

Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space.
Proceedings of the IEEE European Test Symposium, 2024

6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Towards SEU Fault Propagation Prediction with Spatio-Temporal Graph Convolutional Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation.
J. Electron. Test., April, 2023

Towards Reconfigurable CNN Accelerator for FPGA Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Low Complexity Radar Gesture Recognition Using Synthetic Training Data.
Sensors, 2023

Fully Parallel Fully Unrolled BP Decoding of LDPC and Polar Codes.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

Gesture Recognition Using Multiple mmWave FMCW Radars.
Proceedings of the 98th IEEE Vehicular Technology Conference, 2023

Amplitude- and phase-modulated PSSS for wide bandwidth mixed analog-digital baseband processors in THz communication.
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Adaptive Lock-Step System for Resilient Multiprocessing Architectures.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

PULP Fiction No More - Dependable PULP Systems for Space.
Proceedings of the IEEE European Test Symposium, 2023


Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Machine Learning-driven EDAC Method for Space-Application Memory.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

Bits, Flips and RISCs.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

SET and SEU Hardened Clock Gating Cell.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors.
J. Circuits Syst. Comput., December, 2022

A design concept for radiation hardened RADFET readout system for space applications.
Microprocess. Microsystems, April, 2022

Solar Particle Event and Single Event Upset Prediction from SRAM-Based Monitor and Supervised Machine Learning.
IEEE Trans. Emerg. Top. Comput., 2022

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting.
IEEE Access, 2022

Novel Approach for Gesture Recognition Using mmWave FMCW RADAR.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022

Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022

High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS.
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022

An Improved Stage-Combined Belief Propagation Decoding of Polar Codes.
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022

1542 Gbps Fully Pipelined Fast-SSC Decoding of Polar Codes.
Proceedings of the 2022 IEEE 33rd Annual International Symposium on Personal, 2022

FPGA-Based Acceleration of Convolutional Neural Network for Gesture Recognition Using mm-Wave FMCW Radar.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

Laser Fault Injection Attacks against Radiation Tolerant TMR Registers.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

On the SCA Resistance of Crypto IP Cores.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Low Computational Complexity Algorithm for Hand Gesture Recognition using mmWave RADAR.
Proceedings of the 18th International Symposium on Wireless Communication Systems, 2022

A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS.
Proceedings of the 2022 Joint European Conference on Networks and Communications & 6G Summit, 2022

Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022


2021
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters.
CoRR, 2021

Machine Learning Approach for Accelerating Simulation-based Fault Injection.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Reliability Analysis in Less than 200 Lines of Code.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Power- and Area-optimized Neural Network IC-Design for Academic Education.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Classification of Space Particle Events using Supervised Machine Learning Algorithms.
Proceedings of the 8th IEEE International Conference on Data Science and Advanced Analytics, 2021

A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs.
IEEE Trans. Circuits Syst., 2020

Double cell upsets mitigation through triple modular redundancy.
Microelectron. J., 2020

Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches.
J. Circuits Syst. Comput., 2020

Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.
Proceedings of the VLSI-SoC: Design Trends, 2020

Fault Tolerant Platform for Communication and Distance Measurement in Highly Automated Driving.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Recognition of Objects in the Urban Environment using R-CNN and YOLO Deep Learning Algorithms.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

PISA: Power-robust Multiprocessor Design for Space Applications.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Characterization of Single Event Transient Effects in Standard Delay Cells.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Review of Particle Detectors for Space-Borne Self-Adaptive Fault-Tolerant Systems.
Proceedings of the IEEE East-West Design & Test Symposium, 2020

Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Design of Radiation Hardened RADFET Readout System for Space Applications.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
Simulation-based Verification of the Youngest-First Round-Robin Core Gating Pattern.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Selective Fault Tolerance by Counting Gates with Controlling Value.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Radiation Tolerant 10/100 Ethernet Transceiver for Space Applications.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Particle Detector Based on Pulse Stretching Inverter Chain.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

SWIELD: An In Situ Approach for Adaptive Low Power and Error-Resilient Operation.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree.
Microelectron. Reliab., 2018

Study of the operation and SET robustness of a CMOS pulse stretching circuit.
Microelectron. Reliab., 2018

Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Power/Area-Optimized Fault Tolerance for Safety Critical Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Reliability Safety and Security of the Electronics in Automated Driving Vehicles - Joint Lab Lecturing Approach.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Methodology to Verify Digital IP's within Mixed-Signal Systems.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
A substrate noise reduction methodology based on power domain separation of GALS subcomponents.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Asynchronous and GALS Design -Overview and Perspectives.
Proceedings of the New Generation of CAS, 2017

Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Design of an On-chip System for the SET Pulse Width Measurement.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

An analysis of the operation and SET robustness of a CMOS pulse stretching circuit.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Enhanced architectures for soft error detection and correction in combinational and sequential circuits.
Microelectron. Reliab., 2016

An Early Stage Design Flow for Switching Noise Attenuation.
J. Circuits Syst. Comput., 2016

Implementation of a real time unit for satellite applications.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Implementation of DBFN processor for Synthetic Aperture Radar application.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Automatic Clock: A Promising Approach toward GALSification.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Reducing Power Consumption in Fault Tolerant ASICs.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

A survey about testing asynchronous circuits.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A Design Preconditioning Flow for Low-Noise Circuits.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Design Flow for Radhard TMR Flip-Flops.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Traffic Data Collection Using Tire Pressure Monitoring System.
Proceedings of the Telematics - Support for Transport, 2014

Low-power design methodology for CML and ECL circuits.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

GALS design of ECC against side-channel attacks - A comparative study.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Investigating Core-Level N-Modular Redundancy in Multiprocessors.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Evaluating Tire Pressure Monitoring System for traffic management purposes - Simulation study.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

Improved circuitry for soft error correction in combinational logic in pipelined designs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Fault tolerant implementation of a SpaceWire interface.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Increasing multiprocessor lifetime by Youngest-First Round-Robin core gating patterns.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
An Early Termination Strategy for Irregular LDPC Codes with Layered Decoding - Performance Evaluation and Implementation.
Proceedings of the ISWCS 2013, 2013

Design of a low-power asynchronous elliptic curve cryptography coprocessor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Automated integration of fault injection into the ASIC design flow.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

GALS Design for Spectral Peak Attenuation of Switching Current.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
Int. J. Embed. Real Time Commun. Syst., 2012

Performance and complexity analysis of channel coding schemes for multi-Gbps wireless communications.
Proceedings of the 23rd IEEE International Symposium on Personal, 2012

Platform for automated HW/SW co-verification, testing and simulation of microprocessors.
Proceedings of the 13th Latin American Test Workshop, 2012

Applying tire pressure monitoring devices for traffic management purposes.
Proceedings of the International Symposium on Signals, Systems, and Electronics, 2012

Asynchronous circuit design: From basics to practical applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Exploring pausible clocking based GALS design for 40-nm system integration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Performance Analysis of GALS Datalink Based on Pausible Clocking.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Scalable design of a programmable NMR voter with inputs' state descriptor and self-checking capability.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
MAC and baseband processors for RF-MIMO WLAN.
EURASIP J. Wirel. Commun. Netw., 2011

Overview on ATE Test and Debugging Methods for Asynchronous Circuits.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Low-complexity integrated circuit aging monitor.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Design of a Test Processor for Asynchronous Chip Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

GALS Design for On-chip Ground Bounce Suppression.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach.
J. Low Power Electron., 2010

On-line testing of bundled-data asynchronous handshake protocols.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Baseband processor for RF-MIMO WLAN.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

A GALS FFT processor with clock modulation for low-EMI applications.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
GALS for Bursty Data Transfer based on Clock Coupling.
Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

Modeling and Reducing EMI in GALS and Synchronous Systems.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

An OFDM Baseband Receiver for Short-range Communication at 60 GHz.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Ultra low cost asynchronous handshake checker.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Analysis and optimization of pausible clocking based GALS design.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

60GHz OFDM hardware demonstrators in SiGe BiCMOS: State-of-the-art and future development.
Proceedings of the IEEE 19th International Symposium on Personal, 2008

2007
Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture.
IEEE Trans. Wirel. Commun., 2007

Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook.
IEEE Des. Test Comput., 2007

60 GHz SiGe-BiCMOS Radio for OFDM Transmission.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture.
IEEE Trans. Circuits Syst. Video Technol., 2005

A mid-value select voter.
Microelectron. Reliab., 2005

Enhanced GALS Techniques for Datapath Applications.
Proceedings of the Integrated Circuit and System Design, 2005

BIST Technique for GALS Systems.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Request-Driven GALS Technique for Wireless Communication System.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

Hazard Detection in a GALS Wrapper: A Case Study.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
A 16-bit CORDIC rotator for high-speed wireless LAN.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

GALSification of IEEE 802.11a Baseband Processor.
Proceedings of the Integrated Circuit and System Design, 2004

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
New GALS Technique for Datapath Architectures.
Proceedings of the Integrated Circuit and System Design, 2003

Optimized low-power synchronizer design for the IEEE 802.11a standard.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003


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