Milo Tomasevic

According to our database1, Milo Tomasevic authored at least 28 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A lightweight framework for cyber risk management in Western Balkan higher education institutions.
PeerJ Comput. Sci., 2024

2022
Automatic Database Troubleshooting of Azure SQL Databases.
IEEE Trans. Cloud Comput., 2022

Improving performance of background subtraction on mobile devices: a parallel approach.
J. Real Time Image Process., 2022

Comparison of parallel central processing unit- and graphics processing unit-based implementations of greedy string tiling algorithm for source code plagiarism detection.
Concurr. Comput. Pract. Exp., 2022

2019
Double Time-Memory Trade-Off in OSK RFID Protocol.
Wirel. Pers. Commun., 2019

2017
Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture.
Parallel Comput., 2017

Chapter One - A Systematic Approach to Generation of New Ideas for PhD Research in Computing.
Adv. Comput., 2017

2016
Interconnection Networks in Petascale Computer Systems: A Survey.
ACM Comput. Surv., 2016

2015
Graphical processing unit-based parallelization of the Open Shortest Path First and Border Gateway Protocol routing protocols.
Concurr. Comput. Pract. Exp., 2015

2014
Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study.
Adv. Comput., 2014

Register-Level Communication in Speculative Chip Multiprocessors.
Adv. Comput., 2014

2013
An analysis of chain characteristics in the cryptanalytic TMTO method.
Theor. Comput. Sci., 2013

Evaluation and analysis of an on-line error detection monitoring technique.
Comput. Electr. Eng., 2013

Parallelizing general histogram application for CUDA architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

2012
Evolution and trends in GPU computing.
Proceedings of the 2012 Proceedings of the 35th International Convention, 2012

Comparative performance evaluation of the AVL and red-black trees.
Proceedings of the Balkan Conference in Informatics, 2012, 2012

2009
A Simulation Environment for the On-Line Monitoring of a Fault Tolerant Flight Control Computer.
Proceedings of the First IEEE Eastern European Conference on the Engineering of Computer Based Systems, 2009

1999
A hardware implementation of the mechanism of multiprocessing.
Microprocess. Microsystems, 1999

The Interactive Development and Testing System for a RISC-Style Processor.
Comput. J., 1999

1998
An operating system accelerator.
J. Syst. Archit., 1998

1996
The word-invalidate cache coherence protocol.
Microprocess. Microsystems, 1996

Distributed shared memory: concepts and systems.
IEEE Parallel Distributed Technol. Syst. Appl., 1996

A simulation study of hardware-oriented DSM approaches.
IEEE Parallel Distributed Technol. Syst. Appl., 1996

1995
Improved RMS for the PC environment.
Microprocess. Microsystems, 1995

A survey of distributed shared memory systems.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

A simulation-based comparison of two reflective memory approaches.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
Hardware approaches to cache coherence in shared-memory multiprocessors. 2.
IEEE Micro, 1994

Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1.
IEEE Micro, 1994


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