Milo M. K. Martin

According to our database1, Milo M. K. Martin authored at least 53 papers between 1997 and 2022.

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Bibliography

2022

2021
CliqueMap: productionizing an RMA-based distributed caching system.
Proceedings of the ACM SIGCOMM 2021 Conference, Virtual Event, USA, August 23-27, 2021., 2021

2020
1RMA: Re-envisioning Remote Memory Access for Multi-tenant Datacenters.
Proceedings of the SIGCOMM '20: Proceedings of the 2020 Annual conference of the ACM Special Interest Group on Data Communication on the applications, 2020

2016
Top Picks from the 2015 Computer Architecture Conferences.
IEEE Micro, 2016

2015

Everything You Want to Know About Pointer-Based Checking.
Proceedings of the 1st Summit on Advances in Programming Languages, 2015

2014
Synthesizing Finite-State Protocols from Scenarios and Requirements.
Proceedings of the Hardware and Software: Verification and Testing, 2014

WatchdogLite: Hardware-Accelerated Compiler-Based Pointer Checking.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

2013
Designing for Responsiveness with Computational Sprinting.
IEEE Micro, 2013

Utilizing Dark Silicon to Save Energy with Computational Sprinting.
IEEE Micro, 2013

Hardware-Enforced Comprehensive Memory Safety.
IEEE Micro, 2013

Formal verification of SSA-based optimizations for LLVM.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2013

TRANSIT: specifying protocols with concolic snippets.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2013

Ironclad C++: a library-augmented type-safe subset of c++.
Proceedings of the 2013 ACM SIGPLAN International Conference on Object Oriented Programming Systems Languages & Applications, 2013

Syntax-guided synthesis.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

Computational sprinting on a hardware/software testbed.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
Why on-chip cache coherence is here to stay.
Commun. ACM, 2012

Formalizing the LLVM intermediate representation for verified program transformations.
Proceedings of the 39th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2012

Multicore acceleration of priority-based schedulers for concurrency bug detection.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012

Watchdog: Hardware for safe and secure manual memory management and full memory safety.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Computational sprinting.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

An Axiomatic Memory Model for POWER Multiprocessors.
Proceedings of the Computer Aided Verification - 24th International Conference, 2012

2011
Litmus tests for comparing memory consistency models: how long do they need to be?
Proceedings of the 48th Design Automation Conference, 2011

2010
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically.
login Usenix Mag., 2010

Token tenure and PATCH: A predictive/adaptive token-counting hybrid.
ACM Trans. Archit. Code Optim., 2010

CETS: compiler enforced temporal safety for C.
Proceedings of the 9th International Symposium on Memory Management, 2010

RETCON: transactional repair without replay.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Generating Litmus Tests for Contrasting Memory Consistency Models.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
SoftBound: highly compatible and complete spatial memory safety for c.
Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009

InvisiFence: performance-transparent memory ordering in conventional multiprocessors.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Token tenure: PATCHing token counting using directory-based cache coherence.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Hardbound: architectural support for spatial safety of the C programming language.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
NoSQ: Store-Load Communication without a Store Queue.
IEEE Micro, 2007

CheckFence: checking consistency of concurrent data types on relaxed memory models.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Making the fast case common and the uncommon case simple in unbounded transactional memory.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Subtleties of Transactional Memory Atomicity Semantics.
IEEE Comput. Archit. Lett., 2006

Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study.
Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset.
SIGARCH Comput. Archit. News, 2005

Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement.
Proceedings of the Verification, 2005

Scalable Store-Load Forwarding via Store Queue Index Prediction.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Formal Verification and its Impact on the Snooping versus Directory Protocol Debate.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Improving Multiple-CMP Systems Using Token Coherence.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Using Speculation to Simplify Multiprocessor Design.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Token Coherence: A New Framework for Shared-Memory Multiprocessors.
IEEE Micro, 2003

Simulating a $2M Commercial Server on a $2K PC.
Computer, 2003

Token Coherence: Decoupling Performance and Correctness.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol.
IEEE Trans. Parallel Distributed Syst., 2002

SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Bandwidth Adaptive Snooping.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000
Timestamp snooping: an approach for extending SMPs.
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000

1997
Exploiting Dead Value Information.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997


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