Milagros Sashikánth

According to our database, Milagros Sashikánth authored at least 8 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A function generator-based reconfigurable system.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.

Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.

E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004