Mikio Asakura

According to our database, Mikio Asakura authored at least 5 papers between 1990 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1996

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.

Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.

Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.

Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

IEEE J. Solid State Circuits, April, 1994

1990

The cache DRAM architecture: a DRAM with an on-chip cache memory.

Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima

IEEE Micro, 1990