Mikio Asakura

According to our database, Mikio Asakura authored at least 10 papers between 1989 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.

Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.

Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki

IEEE J. Solid State Circuits, 1996

1994

An experimental 256-Mb DRAM with boosted sense-ground scheme.

Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, November, 1994

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.

Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima

IEEE J. Solid State Circuits, April, 1994

1992

A 34-ns 16-Mb DRAM with controllable voltage down-converter.

Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima

IEEE J. Solid State Circuits, July, 1992

Cell-plate line connecting complementary bit-line (C³) architecture for battery-operated DRAMs.

Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima

IEEE J. Solid State Circuits, April, 1992

1991

A circuit design of intelligent cache DRAM with automatic write-back capability.

Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima

IEEE J. Solid State Circuits, April, 1991

1990

An experimental 1-Mbit cache DRAM with ECC.

Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima

IEEE J. Solid State Circuits, February, 1990

The cache DRAM architecture: a DRAM with an on-chip cache memory.

Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima

IEEE Micro, 1990

1989

Twisted bit-line architectures for multi-megabit DRAMs.

Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara

IEEE J. Solid State Circuits, February, 1989