Mikio Asakura

According to our database1, Mikio Asakura authored at least 9 papers between 1989 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1989
1990
1991
1992
1993
1994
1995
1996
0
1
2
3
2
2
2
2
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1996
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.
IEEE J. Solid State Circuits, 1996

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.
IEEE J. Solid State Circuits, 1996

1994
An experimental 256-Mb DRAM with boosted sense-ground scheme.
IEEE J. Solid State Circuits, November, 1994

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits, April, 1994

1992
A 34-ns 16-Mb DRAM with controllable voltage down-converter.
IEEE J. Solid State Circuits, July, 1992

Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1992

1990
An experimental 1-Mbit cache DRAM with ECC.
IEEE J. Solid State Circuits, February, 1990

The cache DRAM architecture: a DRAM with an on-chip cache memory.
IEEE Micro, 1990

1989
Twisted bit-line architectures for multi-megabit DRAMs.
IEEE J. Solid State Circuits, February, 1989


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