Mikio Asakura
According to our database1,
Mikio Asakura
authored at least 9 papers
between 1989 and 1996.
Collaborative distances:
Collaborative distances:
Timeline
1989
1990
1991
1992
1993
1994
1995
1996
0
1
2
3
2
2
2
2
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
1996
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.
IEEE J. Solid State Circuits, 1996
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs.
IEEE J. Solid State Circuits, 1996
1994
IEEE J. Solid State Circuits, November, 1994
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits, April, 1994
1992
IEEE J. Solid State Circuits, July, 1992
Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1992
1990
IEEE J. Solid State Circuits, February, 1990
1989
IEEE J. Solid State Circuits, February, 1989