Miki Tanaka

Orcid: 0009-0003-0739-1876

According to our database1, Miki Tanaka authored at least 25 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Hoare Logic for Diverging Programs.
Arch. Formal Proofs, 2023

Pancake: Verified Systems Programming Made Sweeter.
Proceedings of the 12th Workshop on Programming Languages and Operating Systems, 2023

Enhanced Security against Adversarial Examples Using a Random Ensemble of Encrypted Vision Transformer Models.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022
On the Adversarial Transferability of ConvMixer Models.
CoRR, 2022

On the Transferability of Adversarial Examples between Encrypted Models.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2022

A Detection Method of Temporally Operated Videos Using Robust Hashing.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021
A Detection Method of Operated Fake-Images Using Robust Hashing.
J. Imaging, 2021

Fake-image detection with Robust Hashing.
Proceedings of the 3rd IEEE Global Conference on Life Sciences and Technologies, 2021

A universal detector of CNN-generated images using properties of checkerboard artifacts in the frequency domain.
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020
CycleGAN without checkerboard artifacts for counter-forensics of fake-image detection.
CoRR, 2020

A 29.2 Mb/mm<sup>2</sup> Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2018
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2016
A 6.05-Mb/mm<sup>2</sup> 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
1.8 Mbit/mm<sup>2</sup> ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2015

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2008
Category Theoretic Semantics for Typed Binding Signatures with Recursion.
Fundam. Informaticae, 2008

2007
Formal Proof of Provable Security by Game-Playing in a Proof Assistant.
Proceedings of the Provable Security, 2007

2006
A Unified Category-theoretic Semantics for Binding Signatures in Substructural Logics.
J. Log. Comput., 2006

Pseudo-distributive laws and axiomatics for variable binding.
High. Order Symb. Comput., 2006

Axiomatics for Data Refinement in Call by Value Programming Languages.
Proceedings of the Irish Conference on the Mathematical Foundations of Computer Science and Information Technology, 2006

2005
Binding Signatures for Generic Contexts.
Proceedings of the Typed Lambda Calculi and Applications, 7th International Conference, 2005

A unified category-theoretic formulation of typed binding signatures.
Proceedings of the ACM SIGPLAN International Conference on Functional Programming, 2005

2000
Abstract Syntax and Variable Binding for Linear Binders.
Proceedings of the Mathematical Foundations of Computer Science 2000, 2000


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