Mikhail M. Chupilko

According to our database1, Mikhail M. Chupilko authored at least 14 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2023
High-Level Synthesis versus Hardware Construction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2019
Open-Source Validation Suite for RISC-V.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2018
Test Program Generator MicroTESK for RISC-V.
Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

2017
Maintaining ISA Specifications in MicroTESK Test Program Generator.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

MicroTESK: Specification-Based Tool for Constructing Test Program Generators.
Proceedings of the Hardware and Software: Verification and Testing, 2017

2016
Testing logic circuits at different abstraction levels: An experimental evaluation.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

ESL design with RTL-verified predesigned abstract communication channels.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

2014
Extensible environment for test program generation for microprocessors.
Program. Comput. Softw., 2014

2013
Runtime Verification Based on Executable Models: On-the-Fly Matching of Timed Traces
Proceedings of the Proceedings Eighth Workshop on Model-Based Testing, 2013

2012
Developing test systems for multi-modules hardware designs.
Program. Comput. Softw., 2012

2011
Survey of modern technologies of simulation-based verification of hardware.
Program. Comput. Softw., 2011

A TLM-based approach to functional verification of hardware components at different abstraction levels.
Proceedings of the 12th Latin American Test Workshop, 2011

2010
Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models.
Proceedings of the 2010 East-West Design & Test Symposium, 2010


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