Mike Peng Li
Affiliations:- Intel Corporation, SerDes, high-speed I/O, HSIO, Santa Clara, CA, USA
- Altera Corporation, San Jose, CA, USA
- Wavecrest Corporation, CTO, San Jose, CA, USA (2000-2007)
- University of Washington, Department of Electrical Engineering, Seattle, WA, USA (2010-2020)
- University of Alabama in Huntsville, UAH, Huntsville, AL, USA (PhD 1991)
According to our database1,
Mike Peng Li
authored at least 26 papers
between 1999 and 2025.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2012, "For contributions to the design of jitter test technologies".
Timeline
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Bibliography
2025
IEEE J. Solid State Circuits, January, 2025
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.
IEEE J. Solid State Circuits, 2023
2022
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2014
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
2013
Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013).
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing.
Proceedings of the 2012 IEEE International Test Conference, 2012
2009
New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing.
Proceedings of the 2009 IEEE International Test Conference, 2009
Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps.
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Proceedings of the 2007 IEEE International Test Conference, 2007
2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2004
Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Is "Design to Production" The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999