Mike O'Connor

Proc. ACM Meas. Anal. Comput. Syst., 2018

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency.

[BibT_eX]

[DOI]

Kevin K. Chang

CoRR, 2018

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction.

[BibT_eX]

[DOI]

Donghyuk Lee

Niladrish Chatterjee

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms.

[BibT_eX]

[DOI]

Kevin K. Chang

Proc. ACM Meas. Anal. Comput. Syst., 2017

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2017

Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms.

[BibT_eX]

[DOI]

Kevin K. Chang

CoRR, 2017

Toward standardized near-data processing with unrestricted data placement for GPUs.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2017

Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Architecting an Energy-Efficient DRAM System for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism.

[BibT_eX]

[DOI]

CoRR, 2016

CLARA: Circular Linked-List Auto and Self Refresh Architecture.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

Designing Efficient Heterogeneous Memory Architectures.

[BibT_eX]

[DOI]

IEEE Micro, 2015

Toggle-Aware Compression for GPUs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

Flexible software profiling of GPU architectures.

[BibT_eX]

[DOI]

Mark Stephenson

Siva Kumar Sastry Hari

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

A variable warp size architecture.

[BibT_eX]

[DOI]

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Priority-based cache allocation in throughput processors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Unlocking bandwidth for GPUs in CC-NUMA systems.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

MemcachedGPU: scaling-up scale-out key-value stores.

[BibT_eX]

[DOI]

Tayler H. Hetherington

Proceedings of the Sixth ACM Symposium on Cloud Computing, 2015

Page Placement Strategies for GPUs within Heterogeneous Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication.

[BibT_eX]

[DOI]

Earl E. Swartzlander Jr.

Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014

Cache Coherence for GPU Architectures.

[BibT_eX]

[DOI]

IEEE Micro, 2014

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches.

[BibT_eX]

[DOI]

IEEE Micro, 2014

Learning your limit: managing massively multithreaded caches through scheduling.

[BibT_eX]

[DOI]

Commun. ACM, 2014

Scaling the Power Wall: A Path to Exascale.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2014

Managing DRAM Latency Divergence in Irregular GPGPU Applications.

[BibT_eX]

[DOI]

Rajeev Balasubramonian

Proceedings of the International Conference for High Performance Computing, 2014

A scalable multi-path microarchitecture for efficient GPU control flow.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Cache-Conscious Thread Scheduling for Massively Multithreaded Processors.

[BibT_eX]

[DOI]

IEEE Micro, 2013

Divergence-aware warp scheduling.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Resilient die-stacked DRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

GPUDet: a deterministic GPU architecture.

[BibT_eX]

[DOI]

Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Cache-Conscious Wavefront Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems.

[BibT_eX]

[DOI]

Tayler H. Hetherington

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

Accelerated processing and the Fusion System Architecture.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2006

Network Communication as a Service-Oriented Capability.

[BibT_eX]

Proceedings of the High Performance Computing and Grids in Action, 2006

2001

The iFlow Address Processor.

[BibT_eX]

[DOI]

Christopher A. Gomez

IEEE Micro, 2001

1999

Performance analysis and validation of the picoJava processor.

[BibT_eX]

[DOI]

Sudheendra Hangal

IEEE Micro, 1999

1998

PicoJava: A Direct Execution Engine For Java Bytecode.

[BibT_eX]

[DOI]

Harlan McGhan

Computer, 1998

Tracking Web Usage with Network Flight Recorder.

[BibT_eX]

Chad Childers

Linda Bangert