Mike Hutton

According to our database, Mike Hutton authored at least 43 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2023

Understanding and Mitigating Hardware Failures in Deep Learning Training Systems.

Yi He, Mike Hutton, Steven Chan, Robert De Gruijl, Rama Govindaraju, Nishant Patil, Yanjing Li

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2017

The First 25 Years of the FPL Conference: Significant Papers.

Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang

ACM Trans. Reconfigurable Technol. Syst., 2017

2015

Stratix® 10: 14nm FPGA delivering 1GHz.

Mike Hutton

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Significant papers from the first 25 years of the FPL conference.

Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Arria™ 10 device architecture.

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Design of a high-density SoC FPGA at 20nm.

Brad Vest, Sean Atsatt, Mike Hutton

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2009

FPGA Synthesis and Physical Design.

Mike Hutton, Vaughn Betz

Proceedings of the Embedded Systems Design and Verification, 2009

2008

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.

Yan Lin, Lei He, Mike Hutton

IEEE Trans. Very Large Scale Integr. Syst., 2008

Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs.

André DeHon, Mike Hutton

ACM Trans. Reconfigurable Technol. Syst., 2008

2007

Efficient Timing Analysis With Known False Paths Using Biclique Covering.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Statistical placement for FPGAs considering.

Yan Lin, Mike Hutton, Lei He

IET Comput. Digit. Tech., 2007

Accelerating pattern matching for DPI.

Jun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic

Proceedings of the 2007 IEEE International SOC Conference, 2007

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.

Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Equivalence Verification of FPGA and Structured ASIC Implementations.

Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam

Proceedings of the FPL 2007, 2007

An FPGA Based Memory Efficient Shared Buffer Implementation.

Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic

Proceedings of the FPL 2007, 2007

Integrating FPGAs in high-performance computing: introduction.

Paul Chow, Mike Hutton

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

2006

Timing model reduction for hierarchical timing analysis.

Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Placement and Timing for FPGAs Considering Variations.

Mike Hutton, Yan Lin, Lei He

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Architecture Design Methodology.

Mike Hutton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.

Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A methodology for FPGA to structured-ASIC synthesis and verification.

Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Challenges and opportunities for low power FPGAs in nanometer technologies.

Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Improving the efficiency of static timing analysis with false paths.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Coping With Uncertainty in FPGA Architecture Design.

Boris Ratchev, Mike Hutton, David Mendel

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

The Stratix II logic and routing architecture.

David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Efficient static timing analysis and applications using edge masks.

Mike Hutton, David Karchmer, Bryan Archell, Jason Govig

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Advances and trends in FPGA design.

Mike Hutton

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Architecture and CAD for FPGAs.

Mike Hutton

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Improving FPGA Performance and Area Using an Adaptive Logic Module.

Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini

Proceedings of the Field Programmable Logic and Application, 2004

MAX II: A low-cost, high-performance LUT-based CPLD.

Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation.

Joachim Pistorius, Mike Hutton

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002

Automatic generation of synthetic sequential benchmark circuits.

Michael D. Hutton, Jonathan Rose, Derek G. Corneil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Interconnect enhancements for a high-speed PLD architecture.

Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

2001

Interconnect prediction for programmable logic devices.

Michael D. Hutton

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

1999

Applications of clone circuits to issues in physical-design.

Michael D. Hutton, Jonathan Rose

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Equivalence classes of clone circuits for physical-design benchmarking.

Michael D. Hutton, Jonathan Rose

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Characterization and parameterized generation of synthetic combinational benchmark circuits.

Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

Characterization and parameterized generation of digital circuits.

Mike Hutton

PhD thesis, 1997

Generation of Synthetic Sequential Benchmark Circuits.

Michael D. Hutton, Jonathan Rose, Derek G. Corneil

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996

Upward Planning of Single-Source Acyclic Digraphs.

Michael D. Hutton, Anna Lubiw

SIAM J. Comput., 1996

Characterization and Parameterized Random Generation of Digital Circuits.

Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil

Proceedings of the 33st Conference on Design Automation, 1996

1991

Upward Planar Drawing of Single Source Acyclic Digraphs.

Michael D. Hutton, Anna Lubiw

Proceedings of the Second Annual ACM/SIGACT-SIAM Symposium on Discrete Algorithms, 1991