Mike Bichan

According to our database, Mike Bichan authored at least 5 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2022

A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm.

Bahram Zand, Mike Bichan, Alireza Mahmoodi, Mansour Shashaani, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Eric Liu, Nima Soltani, Al Freeman, Rishi Anand, Syed Rubab, Ranjit Khela, Shaham Sharifian, Karl Herterich

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol.

Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2014

A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.

Mike Bichan, Dustin Dunwell, Qiwei Wang, Anthony Chan Carusone

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2008

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing.

Mike Bichan, Anthony Chan Carusone

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links.

Mike Bichan, Anthony Chan Carusone

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007