Mikaël Cassé

According to our database1, Mikaël Cassé authored at least 22 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

2023
Noise modeling using look-up tables and DC measurements for cryogenic applications.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Transport characterization of CMOS-based devices fabricated with isotopically-enriched <sup>28</sup>Si for spin qubit applications.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

MOS technology for quantum computing: recent progress and perspectives for scaling up.
Proceedings of the Device Research Conference, 2021

2018
Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.
Microelectron. Reliab., 2017

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Drain current model for short-channel triple gate junctionless nanowire transistors.
Microelectron. Reliab., 2016

Analog performance of strained SOI nanowires down to 10K.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs.
Proceedings of the European Solid-State Device Research Conference, 2013

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2009
Process dependence of BTI reliability in advanced HK MG stacks.
Microelectron. Reliab., 2009


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