Miguel E. Figueroa

Orcid: 0000-0002-5033-432X

According to our database1, Miguel E. Figueroa authored at least 74 papers between 1991 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Using virtual function replacement to mitigate 0-day attacks in a multi-vendor NFV-based network.
Comput. Networks, 2025

2024
Machine learning controller for data rate management in science DMZ networks.
Comput. Networks, 2024

A Hardware Accelerator for Quantile Estimation of Network Packet Attributes.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
A streaming algorithm and hardware accelerator to estimate the empirical entropy of network flows.
Comput. Networks, December, 2023

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction.
Sensors, January, 2023

JACC-FPGA: A hardware accelerator for Jaccard similarity estimation using FPGAs in the cloud.
Future Gener. Comput. Syst., 2023

A Sketch-Based Algorithm for Network-Flow Entropy Estimation on Programmable Switches Using P4.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Motion-Based Object Location on a Smart Image Sensor Using On-Pixel Memory.
Sensors, 2022

Survey of Cooperative Advanced Driver Assistance Systems: From a Holistic and Systemic Vision.
Sensors, 2022

Superficial white matter bundle atlas based on hierarchical fiber clustering over probabilistic tractography data.
NeuroImage, 2022

Guaranteeing Network Reliability to 0-Day Exploits Using Cost-Effective Heterogeneous Node Migration.
IEEE Access, 2022

2021
Face Recognition on a Smart Image Sensor Using Local Gradients.
Sensors, 2021

A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems.
Sensors, 2021

A High-Throughput Hardware Accelerator for Network Entropy Estimation Using Sketches.
IEEE Access, 2021

Maximizing Network Reliability to 0-Day Exploits Through a Heterogeneous Node Migration Strategy.
IEEE Access, 2021

Post-Measurement Adjustment of the Coincidence Window in Quantum Optics Experiments.
IEEE Access, 2021

2020
Multimodal registration of visible, SWIR and LWIR images in a distributed smart camera system.
Microprocess. Microsystems, 2020

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration.
IEEE Access, 2020

Small Town vs. Big City: A Comparative Study on the Role of Public Libraries in the Development of Smart Communities.
Proceedings of Ongoing Research, 2020

A hardware accelerator for entropy estimation using the top-k most frequent elements.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
An Instrument for Accurate and Non-Invasive Screening of Skin Cancer Based on Multimodal Imaging.
IEEE Access, 2019

Parallel Optimization of Fiber Bundle Segmentation for Massive Tractography Datasets.
Proceedings of the 16th IEEE International Symposium on Biomedical Imaging, 2019

Hardware Acceleration of k-Mer Clustering using Locality-Sensitive Hashing.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

A Hardware Accelerator for Edge Detection in High-Definition Video using Cellular Neural Networks.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Heavy-Hitter Detection Using a Hardware Sketch with the Countmin-CU Algorithm.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Multimodal Image Registration between SWIR and LWIR Images in an Embedded System.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

The role of public libraries in smart, inclusive, and connected communities: current and best practices.
Proceedings of the 19th Annual International Conference on Digital Government Research: Governance in the Data Age, 2018

2017
Fast Automatic Segmentation of White Matter Streamlines Based on a Multi-Subject Bundle Atlas.
Neuroinformatics, 2017

Embedded registration of visible and infrared images in real time for noninvasive skin cancer screening.
Microprocess. Microsystems, 2017

Clustering of Whole-Brain White Matter Short Association Bundles Using HARDI Data.
Frontiers Neuroinformatics, 2017

An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

An embedded system for image segmentation and multimodal registration in noninvasive skin cancer screening.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
Integrating Dynamic-TDMA Communication Channels into COTS Ethernet Networks.
IEEE Trans. Ind. Informatics, 2016

Modeling and Compensating Temperature-Dependent Non-Uniformity Noise in IR Microbolometer Cameras.
Sensors, 2016

An Embedded Hardware Architecture for Real-Time Super-Resolution in Infrared Cameras.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Embedded Multimodal Registration of Visible Images on Long-Wave Infrared Video in Real Time.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
A compact hardware architecture for digital image stabilization using integral projections.
Microprocess. Microsystems, 2015

2014
Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.
Neural Networks, 2014

Interactive segmentation of white-matter fibers using a multi-subject atlas.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Real-Time Digital Video Stabilization on an FPGA.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
FPGA v/s DSP Performance Comparison for a VSC-Based STATCOM Control Application.
IEEE Trans. Ind. Informatics, 2013

All-on-Chip dq-Frame Based D-STATCOM Control Implementation in a Low-Cost FPGA.
IEEE Trans. Ind. Electron., 2013

A digital architecture for real-time nonuniformity correction of infrared focal-plane arrays.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet Networks.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

GPU-Based acceleration of an automatic white matter segmentation algorithm using CUDA.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
FPGA-based Neural Network for Nonuniformity Correction on Infrared Focal Plane Arrays.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Analysis and Compensation of the Effects of Analog VLSI Arithmetic on the LMS Algorithm.
IEEE Trans. Neural Networks, 2011

Subspace-Based Face Recognition on an FPGA.
Proceedings of the Engineering Applications of Neural Networks, 2011

An FPGA-based real-time nonuniformity correction system for Infrared Focal Plane Arrays.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Modern development methods and tools for embedded reconfigurable systems: A survey.
Integr., 2010

An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Image Recognition in Analog VLSI with On-Chip Learning.
Proceedings of the Artificial Neural Networks, 2009

A Reconfigurable Array for Blind Source-separation on an FPGA.
Proceedings of the BIODEVICES 2009, 2009

2008
Blind Source-Separation in Mixed-Signal VLSI Using the InfoMax Algorithm.
Proceedings of the Artificial Neural Networks, 2008

2007
Subspace-Based Face Recognition in Analog VLSI.
Proceedings of the Advances in Neural Information Processing Systems 20, 2007

2006
Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Effects of Analog-VLSI Hardware on the Performance of the LMS Algorithm.
Proceedings of the Artificial Neural Networks, 2006

2005
A reconfigurable VLSI learning array.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
A 19.2 GOPS mixed-signal filter with floating-gate adaptation.
IEEE J. Solid State Circuits, 2004

On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 17 [Neural Information Processing Systems, 2004

2003
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS.
IEEE J. Solid State Circuits, 2003

A 19.2GOPS, 20mW adaptive FIR filter.
Proceedings of the ESSCIRC 2003, 2003

2002
Competitive learning with floating-gate circuits.
IEEE Trans. Neural Networks, 2002

Prolog to adaptive CMOS: from biological inspiration to systems-on-a-chip.
Proc. IEEE, 2002

Adaptive CMOS: from biological inspiration to systems-on-a-chip.
Proc. IEEE, 2002

Adaptive Quantization and Density Estimation in Silicon.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

Field-Programmable Learning Arrays.
Proceedings of the Advances in Neural Information Processing Systems 15 [Neural Information Processing Systems, 2002

2001
A mixed-signal approach to high-performance low-power linear filters.
IEEE J. Solid State Circuits, 2001

2000
A Silicon Primitive for Competitive Learning.
Proceedings of the Advances in Neural Information Processing Systems 13, 2000

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
Architecture Design of Reconfigurable Pipelined Datapaths.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1991
Linear pseudosystolic array for partitioned matrix algorithms.
J. VLSI Signal Process., 1991

A decoupled access/execute processor for matrix algorithms: architecture and programming.
Proceedings of the Application Specific Array Processors, 1991


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