Miguel Corbalan
Affiliations:- imec, Leuven, Belgium
According to our database1,
Miguel Corbalan
authored at least 69 papers
between 1993 and 2019.
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Bibliography
2019
2014
2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories.
Microelectron. Reliab., 2012
Proceedings of the Foundations of Intelligent Systems - 20th International Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the Intelligent Distributed Computing VI - Proceedings of the 6th International Symposium on Intelligent Distributed Computing, 2012
Proceedings of the 5th International Conference on BioMedical Engineering and Informatics, 2012
2011
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011
Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness.
Microelectron. Reliab., 2011
Microelectron. Reliab., 2011
Proceedings of the Ambient Intelligence - Software and Applications, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Statistical characterization of standard cells using design of experiments with response surface modeling.
Proceedings of the 48th Design Automation Conference, 2011
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.
Proceedings of the ARCS 2011, 2011
Variability Aware Sub-Wavelength Lithography Characterization for Robust SRAM Design.
Proceedings of the ARCS 2011, 2011
2010
Proceedings of the Computer and Information Science 2010 [outstanding papers from the 9th ACIS/IEEE International Conference on Computer and Information Science, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the E-Health - First IMIA/IFIP Joint Symposium, 2010
Proceedings of the Intelligent Distributed Computing IV - Proceedings of the 4th International Symposium on Intelligent Distributed Computing, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Variability aware modeling of SoCs: From device variations to manufactured system yield.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.
J. Signal Process. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006
On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
System-level process variability compensation on memory organizations of dynamic applications: a case study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
IEEE Trans. Computers, 2005
Architectural and Physical Design Optimizations for Efficient Intra-tile Communication.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.
Proceedings of the 2005 Design, 2005
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
Proceedings of the 2004 Design, 2004
Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.
Proceedings of the First Conference on Computing Frontiers, 2004
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Proceedings of the 2003 Design, 2003
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.
Proceedings of the 2003 Design, 2003
2002
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002
Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities.
Proceedings of the 2002 Design, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
J. VLSI Signal Process., 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback.
Proceedings of the 36th Conference on Design Automation, 1999
1998
High-level address optimization and synthesis techniques for data-transfer-intensive applications.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998
1997
Architectural exploration and optimization for counter based hardware address generation.
Proceedings of the European Design and Test Conference, 1997
1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
1993
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the European Design Automation Conference 1993, 1993