Michinobu Nakao

According to our database, Michinobu Nakao authored at least 11 papers between 1995 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs.

Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko

IEICE Trans. Electron., 2013

2010

Reduction of Area per Good Die for SoC Memory Built-In Self-Test.

Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2008

Hardware Overhead Reduction for Memory BIST.

Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki

Proceedings of the 2008 IEEE International Test Conference, 2008

Enhancing Transition Fault Model for Delay Defect Diagnosis.

Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2002

Application of High-Quality Built-In Test to Industrial Designs.

Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

At-Speed Built-in Test for Logic Circuits with Multiple Clocks.

Kazumi Hatayama, Michinobu Nakao, Yasuo Sato

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Test Generation for Multiple-Threshold Gate-Delay Fault Model.

Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A BIST approach for very deep sub-micron (VDSM) defects.

Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Low overhead test point insertion for scan-based BIST.

Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997

Accelerated Test Points Selection Method for Scan-Based BIST.

Michinobu Nakao, Kazumi Hatayama, Isao Higashi

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

A parallel sequential test generation system DESCARTES based on real-valued logic simulation.

Hiroshi Date, Michinobu Nakao, Kazumi Hatayama

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995