Michihiro Yamada

According to our database, Michihiro Yamada authored at least 20 papers between 1985 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Best Security Measures to Reduce Cyber-Incident and Data Breach Risks.

Hiroaki Kikuchi, Michihiro Yamada, Kazuki Ikegami, Koji Inui

Proceedings of the Data Privacy Management, Cryptocurrencies and Blockchain Technology, 2021

2019

Development of a Cyber Incident Information Crawler.

Kazuki Ikegami, Michihiro Yamada, Hiroaki Kikuchi, Koji Inui

Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2019

Mathematical Model to Estimate Loss by Cyber Incident in Japan.

Michihiro Yamada, Hiroaki Kikuchi, Naoki Matsuyama, Koji Inui

Proceedings of the 5th International Conference on Information Systems Security and Privacy, 2019

2018

Evaluation and Development of Onomatopoeia CAPTCHAs.

Michihiro Yamada, Riko Shigeno, Hiroaki Kikuchi, Maki Sakamoto

Proceedings of the 16th Annual Conference on Privacy, Security and Trust, 2018

2017

How Much is Risk Increased by Sharing Credential in Group?

Hiroaki Kikuchi, Koichi Niihara, Michihiro Yamada

Proceedings of the Security and Trust Management - 13th International Workshop, 2017

Decision Tree Analysis on Environmental Factors of Insider Threats.

Michihiro Yamada, Koichi Niihara, Hiroaki Kikuchi

Proceedings of the HCI International 2017 - Posters' Extended Abstracts, 2017

Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious Insiders.

Koichi Niihara, Michihiro Yamada, Hiroaki Kikuchi

Proceedings of the Human Aspects of Information Security, Privacy and Trust, 2017

2001

Design methodology of embedded DRAM with virtual-socket architecture.

Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2001

1999

A 5.3-GB/s embedded SDRAM core with slight-boost scheme.

Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.

Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1998

A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.

Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

400-MHz random column operating SDRAM techniques with self-skew compensation.

Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada

IEEE J. Solid State Circuits, 1998

1997

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's.

Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada

IEEE J. Solid State Circuits, 1997

1992

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure.

Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki

IEEE J. Solid State Circuits, December, 1992

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond.

Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada

IEEE J. Solid State Circuits, November, 1991

An Address Maskable Parallel Testing for Ultra High Density DRAMs.

Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM.

Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada

IEEE J. Solid State Circuits, April, 1990

1989

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register.

Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano

IEEE J. Solid State Circuits, October, 1989

1985

Test Pattern Considerations for Fault Tolerant High Density DRAM.

Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano

Proceedings of the Proceedings International Test Conference 1985, 1985