Michihiro Inoue

According to our database1, Michihiro Inoue authored at least 8 papers between 1988 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

1990
1995
2000
2005
2010
2015
0
1
2
3
2
1
2
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Packaging in minimal fab: An integrated semiconductor line from wafer process to packaging process.
Proceedings of the International Conference on IC Design and Technology, 2016

2005
Effect of Mobility on Communication Performance in Overloaded One-Dimensional Cellular Networks.
Proceedings of the Distributed Computing and Internet Technology, 2005

1993
A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's.
IEEE J. Solid State Circuits, November, 1993

A New Testing Acceleration Chip for Low-Cost Memory Tests.
IEEE Des. Test Comput., 1993

1991
A 64-Mb DRAM with meshed power line.
IEEE J. Solid State Circuits, November, 1991

1990
A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers.
IEEE J. Solid State Circuits, February, 1990

A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier.
IEEE J. Solid State Circuits, February, 1990

1988
A 4-Mbit DRAM with 16-bit concurrent ECC.
IEEE J. Solid State Circuits, February, 1988


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