Michiel Steyaert
Orcid: 0000-0001-6398-8325Affiliations:
- Catholic University of Leuven, Belgium
According to our database1,
Michiel Steyaert
authored at least 244 papers
between 1988 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2003, "For contributions to the design of CMOS RF communications circuits.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on kuleuven.be
-
on orcid.org
On csauthors.net:
Bibliography
2023
Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3
Springer, ISBN: 978-3-031-22708-0, 2023
2022
A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2020
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020
Stacking Isolated SC Cores for High-Voltage Wide Input Range Monolithic DC-DC Conversion.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Fully Integrated Switched-Capacitor-Based AC-DC Converter for a 120 V<sub>RMS</sub> Mains Interface.
IEEE J. Solid State Circuits, 2019
Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC-DC Converters.
IEEE J. Solid State Circuits, 2019
A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm<sup>2</sup>.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 7.5 - 42V Input High-VCR Monolithic DC-DC Converter Using Stacked Isolated SC Cores.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-Efficiency.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
A Fully Integrated Switched-Capacitor Based AC-DC Converter for a 120VRMS Mains Interface.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
Design of Soft-Charging Switched-Capacitor DC-DC Converters Using Stage Outphasing and Multiphase Soft-Charging.
IEEE J. Solid State Circuits, 2017
MIMO Switched-Capacitor DC-DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution.
IEEE J. Solid State Circuits, 2017
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017
10.1 A 1.1W/mm<sup>2</sup>-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Highly integrated wavelength-locked Si photonic ring transmitter using direct monitoring of drop-port OMA.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC-DC Converters.
IEEE J. Solid State Circuits, 2016
Wavelength Locking of a Si Ring Modulator Using an Integrated Drop-Port OMA Monitoring Circuit.
IEEE J. Solid State Circuits, 2016
Wavelength locking of a Si photonic ring transmitter using a dithering-based OMA stabilizing feedback loop.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter.
IEEE J. Solid State Circuits, 2015
A Light-Load-Efficient 11/1 Switched-Capacitor DC-DC Converter With 94.7% Efficiency While Delivering 100 mW at 3.3 V.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
20.1 A light-load-efficient 11/1 switched-capacitor DC-DC converter with 94.7% efficiency while delivering 100mW at 3.3V.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
When hardware is free, power is expensive! Is integrated power management the solution?
Proceedings of the ESSCIRC Conference 2015, 2015
A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters.
Proceedings of the ESSCIRC 2014, 2014
Monitoring optical modulation amplitude using a low-power CMOS circuit for thermal control of Si ring transmitters.
Proceedings of the European Conference on Optical Communication, 2014
2013
IEEE J. Solid State Circuits, 2013
Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013
Proceedings of the ESSCIRC 2013, 2013
A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS.
Proceedings of the ESSCIRC 2013, 2013
A monolithic stacked Class-D approach for high voltage DC-AC conversion in standard CMOS.
Proceedings of the ESSCIRC 2013, 2013
2012
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS.
IEEE J. Solid State Circuits, 2012
Analog Building Blocks for Organic Smart Sensor Systems in Organic Thin-Film Transistor Technology on Flexible Plastic Foil.
IEEE J. Solid State Circuits, 2012
1-1-1 MASH Δ Σ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping.
IEEE J. Solid State Circuits, 2012
On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Dual-output capacitive DC-DC converter with power distribution regulator in 90 nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks.
IEEE Trans. Evol. Comput., 2011
Multiple Event Time-to-Digital Conversion-Based Pulse Digitization for a 250 MHz Pulse Radio Ranging Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil.
IEEE J. Solid State Circuits, 2011
Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS.
IEEE J. Solid State Circuits, 2011
A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A monolithic 0.77W/mm<sup>2</sup> power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS.
IEEE J. Solid State Circuits, 2010
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010
An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
A 500 mV 650 pW random number generator in 130 nm CMOS for a UWB localization system.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
A fully integrated 74% efficiency 3.6V to 1.5V 150mW capacitive point-of-load DC/DC-converter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001].
IEEE J. Solid State Circuits, 2009
A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM.
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Ultra low power detection circuits in 130nm CMOS for a wireless UWB localization system.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G<sub>m</sub>-C Biquad in 0.13-mu m CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer.
IEEE J. Solid State Circuits, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system.
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the ESSCIRC 2008, 2008
A fully-integrated Wienbridge topology for ultra-low-power 86ppm/°C 65nm CMOS 6MHz clock reference with amplitude regulation.
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the ESSCIRC 2008, 2008
A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
A fully-integrated 0.18µm CMOS DC-DC step-up converter, using a bondwire spiral inductor.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Microelectron. Reliab., 2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
Positive feedback frequency compensation for low-voltage low-power three-stage amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits.
Microelectron. Reliab., 2004
IEEE J. Solid State Circuits, 2004
IEEE J. Solid State Circuits, 2004
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Two high-speed optical front-ends with integrated photodiodes in standard 0.18 μm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.
Microelectron. Reliab., 2003
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter.
IEEE J. Solid State Circuits, 2003
Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier.
IEEE J. Solid State Circuits, 2003
Proceedings of the ESSCIRC 2003, 2003
Oscillator pulling and synchronisation issues in self-oscillating class D power amplifiers.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 14th International Conference on Digital Signal Processing, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization.
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
The extraction of transistor mismatch parameters: the CMOS current-steering D/A converter as a test structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications.
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique.
IEEE J. Solid State Circuits, 1997
Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's.
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
Int. J. Circuit Theory Appl., 1996
1995
A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology.
IEEE J. Solid State Circuits, December, 1995
IEEE J. Solid State Circuits, December, 1995
IEEE J. Solid State Circuits, July, 1995
IEEE J. Solid State Circuits, July, 1995
A programmable analog cellular neural network CMOS chip for high speed image processing.
IEEE J. Solid State Circuits, March, 1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1994
A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links.
IEEE J. Solid State Circuits, December, 1994
Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages.
IEEE J. Solid State Circuits, August, 1994
Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable Templates.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Low-voltage Analog CMOS Filter Design.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
High-performance CMOS continuous-time filters.
The Kluwer international series in engineering and computer science 223, Kluwer, ISBN: 978-0-7923-9339-9, 1993
1988
IEEE J. Solid State Circuits, June, 1988
IEEE J. Solid State Circuits, June, 1988