Michiaki Muraoka

According to our database, Michiaki Muraoka authored at least 18 papers between 1982 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A critical net reshape-router for high-performance VLSI layout design.

Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A multilayer crosstalk avoidance router using restricted maze grids.

Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2004

A DFT Selection Method for Reducing Test Application Time of System-on-Chips.

Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2004

Design methodology for SoC arthitectures based on reusable virtual cores.

Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.

Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

VCore-based platform for SoC design.

Yoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Synthesis for SoC architecture using VCores.

Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

VCore-based design methodology.

Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

VCDS tool demonstration.

Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A SoC Test Strategy Based on a Non-Scan DFT Method.

Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

1997

A Partial Scan Design Method Based on n-Fold Line-up Structures.

Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Design for testability Method Using RTL Partitioning.

Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Design for testability using register-transfer level partial scan selection.

Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

A State Traversal Algorithm Using a State Covariance Matrix.

Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1985

ACTAS: an accurate timing analysis system for VLSI.

Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1982

Logic simulation for LSI.

Kazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka

Proceedings of the 19th Design Automation Conference, 1982